Dear all,

I noticed a strange phenomenon during jitter simulation of driven circuits (in casu: logic gates). The simulator used was HSPICE RF.
The logic gates were driven by a 50% duty cycle square wave. The number of sidebands was set to 250 and the jitter integration bandwidth  to 5GHz.

During a first set of simulations, I used a load capacitance of 0.1pF. I thought this was a conservative setting which would result in worst-case jitter results.

However, now I noticed that when I decrease the load capacitance to e.g. 0.01pF the reported jitter increases.

To me this is counterintuitive, since from handcalculations I would expect the jitter to decrease with decreasing load capacitance for synchronous (added) jitter by logic gates (e.g. INV, AND...).

Has anyone observed this too? Any (possible) physical explanation?

Regards

Peter

Visjnoe wrote on Jul 10^th, 2008, 2:42am:


Could you please point out a reference or link where I might be able to gain more mathematical insight into the jitter-load capacitance relationship.

Thanks