I met a problem about the voltage regulator. For a plane voltage regulator, we usually use an op-amp and a pmos (output stage) configuration to make negative feedback loop to get the regulated voltage. But why the regulator can regulate  voltage only on the condition that the voltage difference between the source and the drain of the output pmos was smaller than the threshold of the output transistor?
   In the simulation I used a pwl soure to model the source of pmos. I found  that the regulator lost its function when the source volatage exceed some value .
   I expect your help, thank you very much!!

htshang wrote on Jul 13^th, 2008, 12:31am:


It would be much easyier to answer if you could give some figures.
Do you mean that the LDO regulates only if - for example - Vds=2 volts at Vgs= 3volts ?

First of all, thank you very much for all of the you.
Matybe I forgot to point out that the amplifier in my regulator is a current mode one. I do the ac analysis in closed-loop configuration, finding out the phasemargin is good. But when the voltagte difference between source(connect to positive power vext!, I use pwl source to simulate the power-up,for example :VVEXT!  vext!  gnd!  pwl(0 1 3u 5)) and drain(regulator output node)is bigger than threhold voltage(absolute value),then regulator output will track the vext! not stay to vref(regulator input voltage) anymore.
    In my opinion, when the voltage difference is bigger than threshold voltage, the current mode amplifier can not work properly as usual. If the amplifier is a voltage amp, then the matter will disappear. Just as Berti said--a LDO will also work with vds of the power transistor well above threshold.
'     For 'LDO devices vary over 30db in forward path gain as the PMOS transistor goes from saturation to triode region (a function of Vds)@loose-electron' I did not understand.

htshang wrote on Jul 16^th, 2008, 6:09am:


Hi,

What he meant is that since the supply line you are regulating with the LDO can vary over a large range, the operating conditions for the LDO pass transistor could change from triode to saturation mode (triode when the supply line is close to the regulated line voltage, saturation when such voltages difference is large).

Consequently, since the LDO pass transistor is within the loop and the gain associated to its stage is a function of the operating condition, the loop gain can change as much as 30dB and this should be considered when analyzing stability.

Regards
Tosei

Tosei - Nicely stated - thanks for doing my follow up!  :) -- Jerry

HdrChopper wrote on Jul 16^th, 2008, 10:30am: