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Syntax Error when using spectre to simulation verilog-A file. (Read 1887 times)

Julian18

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Posts: 55

Syntax Error when using spectre to simulation verilog-A file.
Jul 20^th, 2008, 3:15am

Hi, there
I am very new to verilog-A field, so bear this simple question. I am runing Ken's sample and hold example and got the error like below:
Quote:

Error found by spectre during AHDL read-in.
"sh.va", line 5: "'<<--? include "discipline.h""
"sh.va", line 5: Error: syntax error
"sh.va", line 11: "electrical Pin,<<--? Nin, Pout, Nout;"
"sh.va", line 11: Error: syntax error

I am just using the spectre from command line(instead of simulating in ADE) and the command is
Quote:

spectre s_and_hold.scs

I wonder if I have to add some options in order for spectre to realize that the file contains verilog-A statements.

TIA.

« Last Edit: Jul 20^th, 2008, 5:43am by Julian18 »

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Syntax Error when using spectre to simulation verilog-A file. Reply #1 - Jul 21^st, 2008, 8:57am Did you ahdl_include "sh.va" in your .scs file? (Or were you using a regular include like for model files?)
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