I'm working on a Verilog-AMS model and want to use functionality similar to VHDL-AMS's ASSERT/REPORT capability to detect and report errors. As an example, I want to check for valid parameter values and report an error if needed (along with stopping design compilation/elaboration). Are there equivalent commands in Verilog-AMS? I know about the $display/$monitor/$strobe commands, but I can't see where any of these helps me with error detection (at least without some additional code) or, more importantly, stopping the compilation/elaboration process.

Thanks in advance...