Designer’s Guide Community

New Member

Offline

Posts: 7
Switzerland

S/H switches for pipelined ADC
Jul 24^th, 2008, 9:43am

I am designing a 10-bit pipelined ADC that will operate at 40MHz with a supply of 1.5V.

To calculate the maximum ON resistance of the switches I have:

1 - Calculated the maximum inclination of a full range (1V) sinusoidal input signal with 20MHz;

2 - Considered a static error to a ramp (with the inclination calculated before) of a RC system, smaller than 1/4 of LSB.

I got the maximum ON resistance of the switch to be 14.5 Ohms for a 500fF capacitor.

Since this resistance is very low I need switches of around W=140u and L=120n.

They look huge to me so I wonder what is your opinion.

If I use bootstrapped switches I can reduce then to half of the size.

Thanks for your help,

Hugo

Back to top

IP Logged

Berti Community Fellow Offline Posts: 356	Re: S/H switches for pipelined ADC Reply #1 - Jul 25^th, 2008, 3:46am I think you did a mistake in your calculation. From a rough estimation I think that Ron=1kΩ should do the job. Cheers
Back to top	IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: S/H switches for pipelined ADC Reply #2 - Jul 28^th, 2008, 1:33pm Why dont you put the sampling circuit together in a simulation and try it out? Do your switch sizing in the slow/weak corners for the MOS, and the 20% high corner for the capacitance value, to get the worst case RC time constant.
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

ywguo

Community Fellow

Offline

Posts: 943
Shanghai, PRC

Re: S/H switches for pipelined ADC
Reply #3 - Jul 29^th, 2008, 2:31am

Hi Hugo,

That is a too tight specification. I am not clear your point. Would you please explain it?
Based on my understanding, that is not reasonable because it is not necessary for an S/H to capture very very fast in order to keep the error smaller than 1/4 LSB at any time. We just need it to settle within the specified error, say 1/4 LSB, at the end of the sampling phase.

Best regards,
Yawei

Back to top

IP Logged

HugoFranca

New Member

Offline

Posts: 7
Switzerland

Re: S/H switches for pipelined ADC
Reply #4 - Jul 29^th, 2008, 6:29am

Thank you for the answers.

I think that my specifications was too tight and that I have now a clearer picture of the problem.

The switches and the sampling capacitor are equivalent to a low pass filter at the input of the ADC. If I calculate the Ron for a bandwidth of 100MHz (5 times the Nyquist freq.) I get a Ron of 636Ω.
This filter has very little influence in my 20MHz max. input freq in terms of gain, however it introduces a little phase (around 1 degree).
This little degree causes the input signal and the sampled signal to have a difference bigger than 1 LSB for the zero crossing points!
If I want this difference to be below 1/4LSB, the bandwidth of the sampling RC needs to be 4.4GHz, which corresponds to a Ron=14.5Ω!

So I think that I will ignore this small phase that is introduced and use switches with Ron of around 200Ω which are easy to do.

The circuit will NOT settle within, say 1/4LSB, at the end of the sampling phase, but I think that there is no big deal with this, right?

Cheers,
Hugo

Back to top

IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: S/H switches for pipelined ADC
Reply #5 - Jul 30^th, 2008, 12:12am

HugoFranca wrote on Jul 29^th, 2008, 6:29am:

Thank you for the answers.

I think that my specifications was too tight and that I have now a clearer picture of the problem.

So I think that I will ignore this small phase that is introduced and use switches with Ron of around 200Ω which are easy to do.

The circuit will NOT settle within, say 1/4LSB, at the end of the sampling phase, but I think that there is no big deal with this, right?

Cheers,
Hugo

I am afraid that your understanding of the specs is still wrong. While the value of Ron you have chosen seems more reasonable, please bear in mind that an ADC is a sampling system, and switches are nonlinear blocks.

Unless your sampled signal settles to a sufficient accuracy within the sampling phase, you will get horrible distortion, and there is no point building a 10-bit ADC when the sampling switch is only 5-bit accurate.

If you don't believe me, just run a simple transient simulation of the switches and the cap, and look at the spectrum of the sampled signal.

There are 2 design challenges to resolve here, which depend on your application.

1. Settling accuracy for static signals. If there is already a sample-and-hold before your ADC (say), then your ADC will be digitizing static signals, more or less. So, you just need 2*Ron.C such that you have more than 7.7 time constants (for 66 dB settling accuracy) in the sample phase.

2. If you have a dynamic signal on the other hand, and this may be quite fast. You quote 20 MHz input, then the requirements are quite different. There is probably no hope to get good linearity, unless you bootstrap your switch. Because now, your switch timeconstants have to be so small that the switch tracks the changing input all the time. That is probably the reason why you got this 14.5 Ohm number. But with a bootstrapped switch, you will reduce the nonlinearity in the switch Ron, which will allow operation with a tolerable size switch (and a not so tolerable size for the bootstrap capacitor).

3. The nightmarish scenario if you are making a subsampled system, that is, your input signal still has a small bandwidth but the absolute frequency is very high. Then bootstrapped switches are the only way as well, but even they may have a hard time.

So, check if you have scenario 1 or 2 before you begin switch design, and do a transient analysis for distortion.

Regards
Vivek

Back to top

IP Logged

HugoFranca

New Member

Offline

Posts: 7
Switzerland

Re: S/H switches for pipelined ADC
Reply #6 - Jul 30^th, 2008, 8:29am

Dear Vivek,

Thank you for your answer!

I am in the "case 2".
There is no separated S/H in my pipelined ADC, the S/H is done in the first multiplication stage, so the input signal can have a frequency up to 20MHz.

Now, one thing is the linearity of the switch and other is the maximum Ron value.

I was talking about the maximum value of Ron. And my conclusion is that for tracking the input signal within 1/4 LSB error, Ron should be bellow 14.5Ω which is very hard to get even with the bootstrapped switches. I don't see a solution for this and I couldn't find one in your answer.

The problem of the linearity, is another one. The total Ron (3 switches 1 passgate (250mV<Vin<750mV) and 2 NMOS (Vin=750mV) in series) varies between 108Ω and and 122Ω so this will cause some problems of linearity that I didn't measure yet but I think that this will not be the main issue.

Best regards,
Hugo

Back to top

IP Logged

HugoFranca

New Member

Offline

Posts: 7
Switzerland

Re: S/H switches for pipelined ADC
Reply #7 - Jul 30^th, 2008, 8:55am

There was a small mistake with the voltages in my previous message so I will explain better.

The sampling is done with 3 switches in series.

One transmission gate connected between the input and the capacitor.The input signal can be between 250mV and 1250mV and Ron varies between 32Ω and 46Ω.

The 2nd and 3rd are simple NMOS connected in serie between the capacitor and VCM that is fixed to 750mV. Ron of each one is 38Ω.

So the total Ron changes with the input signal between 108Ω and 122Ω.

Hugo

Back to top

IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: S/H switches for pipelined ADC
Reply #8 - Jul 30^th, 2008, 11:44pm

Hi Hugo,

You are right. My post did not give you any real suggestion. Here it is.

1. How accurately your sampled signal tracks your input signal is a spec assuming that you want
an absolute accuracy (offset+distortion) of around 11 bits from your S&H.

2. In reality, you do not need this tracking to be that accurate, if you can accept some offset and gain errors, and you have a switch whose Ron does not vary significantly with signal.

3. Still, I did a calculation assuming that you have to achieve 0.25 LSB tracking accuracy. In track mode, you have an equivalent Ron of all switches (I will call it Rtotal), in series with the sampling cap C. The tracking error = C(dV/dt)*Rtotal. For 0.25 LSB tracking error, you need Rtotal = 78 Ohms for C=0.5 pF, ADC fullscale=1V, and a 1 V sinewave at 20 MHz, and a 10 bit ADC assumed.
This is of course a very small value but would still not result in unit switches requiring 14.5 Ohm Ron. Still, this is impractical for such a small capacitor and such a moderate resolution ADC at this moderate sampling rate. So, ignore this.

4. If you were to make a bootstrapped NMOS switch and control the V(G.S) to be fairly signal-independent, you would have an Ron which would be more or less independent of Vin, leading to a fixed tracking error dV, which would be mostly benign, and some small distortion components. You may be able to use a larger Ron than what you would get from (3) above. In fact, ROn could be much larger, and you can decide how much signal loss you are willing to accept during the tracking phase.

5. If you use a simple transmission gate, you will need to ensure that the Ron is low enough that the variations in it do not cause a distortion larger than your target. Since Ron of a transmission gate is very nonlinear, you can assume that net error calculated in (3) is also the distortion error. So, if you wanted 0.25 LSB distortion from the sampling switch, make Rtotal < 78 Ohm.

One question: Why are you using 3 switches in series instead of 2? Are you doing time-interleaved pipelines with a 3rd master switch? 2 switches in series are bad enough. Also remember that tracking error results from every single switch when the input is a fast changing signal, and not just from the switch between the input and the cap. This should be obvious from the calculation I show in (3). Of course, the voltage levels and Ron variation are smaller for the other switches, but not negligible, as would be if the input were already sampled-and-held.

Regards
Vivek

Back to top

IP Logged

vivkr Community Fellow Offline Posts: 780	Re: S/H switches for pipelined ADC Reply #9 - Jul 30^th, 2008, 11:45pm And one more thing. I would see if it were at all possible to change that VCM to an even lower value. The lower you can work with, the better for using NMOS switches alone to do the job.
Back to top	IP Logged

HugoFranca

New Member

Offline

Posts: 7
Switzerland

Re: S/H switches for pipelined ADC
Reply #10 - Jul 31^st, 2008, 3:12am

Hi Vivek,

Thanks for your reply.
I have calculated again Rtotal using your formula and I got 15.5Ω.
I got 14.5Ω before because I was calculating with a 0.55pF capacitor.
Just to review the calculations I have:

Error = 1V / 512 /4 -- for 1/4 LSB between 1st and 2nd stage
dV/dt(max) = 0.5 sin (2Π * 20000000) = 2Π *10^7

Rtotal = (1/512/4)/(5*10^-13 * 2Π*10^7) = 15.5Ω

I need 3 switches because I using double sampling and the extra switch "syncronizes" the skew of each parallel sampling circuit.

To reduce the VCM is a good idea and I have tried that before but the problem is that it also changes the input CM of the OpAmp and I don't have time to optimize the OpAmp for the new CM because I will submit a prototype in September.
I have the ADC almost ready and I'm doing the layout in paralell with my simulations.

Cheers,
Hugo

Back to top

IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: S/H switches for pipelined ADC
Reply #11 - Jul 31^st, 2008, 5:49am

HugoFranca wrote on Jul 31^st, 2008, 3:12am:

Hi Vivek,

Thanks for your reply.
I have calculated again Rtotal using your formula and I got 15.5Ω.
I got 14.5Ω before because I was calculating with a 0.55pF capacitor.
Just to review the calculations I have:

Error = 1V / 512 /4 -- for 1/4 LSB between 1st and 2nd stage
dV/dt(max) = 0.5 sin (2Π * 20000000) = 2Π *10^7

Rtotal = (1/512/4)/(5*10^-13 * 2Π*10^7) = 15.5Ω

I need 3 switches because I using double sampling and the extra switch "syncronizes" the skew of each parallel sampling circuit.

To reduce the VCM is a good idea and I have tried that before but the problem is that it also changes the input CM of the OpAmp and I don't have time to optimize the OpAmp for the new CM because I will submit a prototype in September.
I have the ADC almost ready and I'm doing the layout in paralell with my simulations.

Cheers,
Hugo

Hi Hugo,

1. A mistake in my calculation. I used 10x lower frequency. So if you were trying to get 0.25 LSB absolute error (@ 10 bit level), you would need 7.8 Ohms.

2. A mistake in your calculations. You are using a 9bit value as reference (512 instead of 1024). So, if you correct this, we both will get the same number ~ 7.75 Ohms or so.

3. I can imagine that it is a little difficult to change the CM level now. So stay with it. Double sampling was also obvious since you are using 3 switches. This is what I refer to as interleaved pipelines, since that's what they are also.

4. You should seriously try bootstrapping. It will be a lifesaver. But first try a simple transient simulation followed by an FFT to see how much distortion you are getting. For a good example of bootstrapping, refer to the JSSC paper by Dessouky & Kaiser, JSSC, Mar. 2001, Fig. 7 (if I remember). It is quite a large switch, mainly due to the bootstrap capacitance, but try to use it sparingly at the most critical places (all switches which are ON in the tracking phase would need it).
Once you have run such a simulation and seen where you are with respect to INL, you can decide what to do. There is no need to reduce absolute error if your switch is linear (bootstrapped).

5. Alternatively, try and see how far you get with just transmission gates. My guess would be that it would be just close enough for 10 bits.

6. The biggest question is also the INL you are willing to tolerate, because the sampling switch will only cause INL and no DNL in a standard sample-and-hold arrangement. For a 10bit ADC, I don't think you are willing to tolerate much INL.

Regards
Vivek

Back to top

IP Logged

ywguo

Community Fellow

Offline

Posts: 943
Shanghai, PRC

Re: S/H switches for pipelined ADC
Reply #12 - Aug 2^nd, 2008, 8:03am

Hi Hugo,

Please simulate the S/H and plot its FFT/fourier analysis result and calculate the THD.

If the settling error for a full scale step response is less than 0.5 LSB, I guess the THD/SNR is less than about 0.5LSB too. In other words, the S/H can achieve about 11 ENOB if the S/H settle to less than 0.5 LSB in the sampling phase, which converts to 7.6 times constants.

For a 40MS/s ADC, the sampling phase is often greater than 10ns. So the time constants should be less than 10ns/7.6=1.32ns. For a 0.5pF cap, the Rtotal = 263 Ω.

Best regards,
Yawei

Back to top

IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: S/H switches for pipelined ADC
Reply #13 - Aug 4^th, 2008, 12:02am

ywguo wrote on Aug 2^nd, 2008, 8:03am:

Hi Hugo,

Please simulate the S/H and plot its FFT/fourier analysis result and calculate the THD.

If the settling error for a full scale step response is less than 0.5 LSB, I guess the THD/SNR is less than about 0.5LSB too. In other words, the S/H can achieve about 11 ENOB if the S/H settle to less than 0.5 LSB in the sampling phase, which converts to 7.6 times constants.

For a 40MS/s ADC, the sampling phase is often greater than 10ns. So the time constants should be less than 10ns/7.6=1.32ns. For a 0.5pF cap, the Rtotal = 263 Ω.

Dear Yawei,

Your calculation implicitly assumes that the input signal is either a DC or is previously sampled-and-held by the preceding stage, because then the input is fixed, and the sampled value approaches it exponentially with a timeconstant given by the RC of the switch-capacitor network, which has the entire phase to settle.

However, Hugo is asking for settling accuracy when tracking a changing input. Here, the sampled output either needs to settle within 0.5 LSB or whatever accuracy level is desired in a much shorter time (if switch Ron is very nonlinear), or else the requirement is different if the switch Ron is almost linear. I think the calculations we both (Hugo and myself) show are correct, but not useful from a practical point of view since one either has to assume that all error that results is nonlinear and overdesign, or else, one assumes all error to be gain error (if switch Ron is 100% linear), and underdesigns a little using a bootstrapped switch.

Your point is perfectly correct that one needs to do an FFT of the transient output to see the THD.
This is the only way to really tell whether the required linearity is achieved or not.

Regards
Vivek

Back to top

IP Logged

Berti

Community Fellow

Offline

Posts: 356

Re: S/H switches for pipelined ADC
Reply #14 - Aug 5^th, 2008, 1:12am

Hi all,

Sorry, but to me this discussion is confusing. I have never seen nor measured a sampling circuit that needs a switch resistance as low as 15Ohms for the relaxed requirements of 40Ms/s and 10bit!

I fully agree with Yawei that 7.6 times the time-constant will do the job, and I don't
see why the sampled signal shouldn't track the input signal (since the RC time constant
is larger than the input signal frequency!)

Thanks for explanations!

Regards

Back to top

IP Logged