Berti wrote on Aug 5th, 2008, 1:12am:Hi all,
Sorry, but to me this discussion is confusing. I have never seen nor measured a sampling circuit that needs a switch resistance as low as 15Ohms for the relaxed requirements of 40Ms/s and 10bit!
I fully agree with Yawei that 7.6 times the time-constant will do the job, and I don't
see why the sampled signal shouldn't track the input signal (since the RC time constant
is larger than the input signal frequency!)
Thanks for explanations!
Regards
Hi Berti,
Yes! the discussion has got a bit confusing. Let me try to clarify:
1. The 7.6 timeconstants allowance for the sampling phase implicitly assumes that the input is fixed for a 66 dB settling accuracy. This would happen if the input were already sampled-and-held.
2. Although the input signal is well within the bandwidth of the switch, the finite Ron combined with the current i(t) = C*dVin/dt will cause a drop dV = i(t)*Ron. Thus, there is a difference to (1). In (1), there is almost no current flowing into the switch at the end of the phase. However, the same is not true when you are applying a continuously varying input to the switch-capacitor-switch arrangement in track mode. There is always current flowing as the signal keeps on changing.
3. By itself, this drop dV would be harmless. If Ron were constant across all inputs of interest, you would have a gain error only => no nonlinear distortion. However, the Ron of a common transmission gate is highly nonlinear. The Ron may easily vary by a factor of 5-10 over input range.
So, one can assume that all error dV caused in this case is distortion, and must size Ron small enough to guarantee that the largest Ron gives small enough dV. Thus, one is forced to make the absolute error dV caused by the switch to be smaller than required nonlinear distortion spec. Hence the fantastically low Ron requirement. You could probably simulate and get an Ron spec about 2x times less tight, depending on the exact amount of nonlinearity from your switch, but you would still need a very large switch.
4. Now, if you have a relatively linear switch such as a bootstrapped switch, then you can assume that dRon across the input range is very small (< 10% of Ron). So the net error introduced by the switch has components dV = dVgain + dVnonlin, where the latter is about 10% of the total error. So you can use an Ron about 10 times or more larger, depending on your bootstrapped switch design.
I hope this makes the point clear. I cannot explain better. The best would be if you were to try to make a simple tracking circuit. You don't even need to turn the switches ON and OFF, just leave the tracking switches permanently ON and look at the voltage across the sampling cap, and take an FFT of this one for a rapidly varying input. Do this for the case where you have a common transmission gate, and for a bootstrapped switch (can be approximated with an NMOS whose gate-source voltage is fixed with an ideal voltage source). This is a very simple comparison but quite revealing.
Otherwise, ask people who have made sample-and-holds. This problem pops up there all the time. I came across it that way myself. The basic point I will emphasize again is that there is always a current flowing through the switch in the track phase when the input is changing all the time, and this is the main culprit.
Regards
Vivek