Berti wrote on Aug 5^th, 2008, 1:12am:


Hi Berti,

Yes! the discussion has got a bit confusing. Let me try to clarify:

1. The 7.6 timeconstants allowance for the sampling phase implicitly assumes that the input is fixed for a 66 dB settling accuracy. This would happen if the input were already sampled-and-held.

2. Although the input signal is well within the bandwidth of the switch, the finite Ron combined with the current i(t) = C*dVin/dt will cause a drop dV = i(t)*Ron. Thus, there is a difference to (1). In (1), there is almost no current flowing into the switch at the end of the phase. However, the same is not true when you are applying a continuously varying input to the switch-capacitor-switch arrangement in track mode. There is always current flowing as the signal keeps on changing.

3. By itself, this drop dV would be harmless. If Ron were constant across all inputs of interest, you would have a gain error only => no nonlinear distortion. However, the Ron of a common transmission gate is highly nonlinear. The Ron may easily vary by a factor of 5-10 over input range.
So, one can assume that all error dV caused in this case is distortion, and must size Ron small enough to guarantee that the largest Ron gives small enough dV. Thus, one is forced to make the absolute error dV caused by the switch to be smaller than required nonlinear distortion spec. Hence the fantastically low Ron requirement. You could probably simulate and get an Ron spec about 2x times less tight, depending on the exact amount of nonlinearity from your switch, but you would still need a very large switch.

4. Now, if you have a relatively linear switch such as a bootstrapped switch, then you can assume that dRon across the input range is very small (< 10% of Ron). So the net error introduced by the switch has components dV = dVgain + dVnonlin, where the latter is about 10% of the total error. So you can use an Ron about 10 times or more larger, depending on your bootstrapped switch design.

I hope this makes the point clear. I cannot explain better. The best would be if you were to try to make a simple tracking circuit. You don't even need to turn the switches ON and OFF, just leave the tracking switches permanently ON and look at the voltage across the sampling cap, and take an FFT of this one for a rapidly varying input. Do this for the case where you have a common transmission gate, and for a bootstrapped switch (can be approximated with an NMOS whose gate-source voltage is fixed with an ideal voltage source). This is a very simple comparison but quite revealing.

Otherwise, ask people who have made sample-and-holds. This problem pops up there all the time. I came across it that way myself. The basic point I will emphasize again is that there is always a current flowing through the switch in the track phase when the input is changing all the time, and this is the main culprit.

Regards
Vivek

It also seems too tight a spec to me.
The non-linear error is taken care of by bootstrapping the switch. There remains the non-linear capacitance, etc, so it's in your best interest to minimize the size of the switch to reduce that contribution w.r.t. the sampling capacitor (which should be *very* linear).

Now, this non-linearity consideration is already mixing some of the initial issues up.
Due to the RC constant of the switch there will always be a difference between the input signal and the voltage on the sampling capacitor.

Simple RC circuit behavior, phase error (so, time delay).

I don't see the point of trying to reduce that phase/delay error to less than one LSB, since the anti-aliasing filter at the input certainly contributes a lot more to this at the Nyquist frequency than what he seems to be designing for.

I usually get a spec for amplitude attenuation at nyquist, say -1dB, and implicitly I have there the phase error (or tracking error) that is acceptable.

I have been playing with the L and W of the transistors of the transmission gate and I got to a point where the difference between Ron max and Ron min is around 3Ω.

Check the figure.

If I add to this the resistences of the 2 NMOS that are in series I get a Ron that varies between 106Ω and 109Ω.

Of course that this range is for a typical process, so it will get worse for the corners SF and FS.

But I think that for now I will not use bootstrapped switches.

Cheers,
Hugo

Hi! everyone!
I'm so glad that finally someone has discussed about the pipelined ADC.
I had designed a 30MHz pipelined ADC before. Some simulation experience may offer some help.
I agree with vivkr and Berti, in S&H simulation, the linearity simulation is needed. Calculation about the switch error just gives a roughly estimation about  the performance. Using FFT test can show the real linearity that you can gain in S&H circuit. In my simulation experience , the bootstraped switches will need to get enough linearity in the spec of 40MHz, 10bit ADC.
Hope this provide some help!