mehregan
Junior Member
![* *](https://designers-guide.org/forum/Templates/Forum/default/starblue.gif)
Offline
Posts: 10
Minnesota
|
Yes, if you think about it, worst-case analysis is really a specification verification problem. If you could do true top-down design and make budgets for all your critical IC and hybrid component parametrics, then you could assure you meet requirements over all worst case conditions .
In more classic bottom up design, corner simulation, monte-carlo and even worst-case types of simulation have been around for many years and are generally accepted. The problem we see typically is that the IC block is designed by an IC designer with assumptions that other blocks and hybrid discrete components are ideal or at worst nominal. Even corner simulations are run assuming nominal discrete components, clocks, etc.
If someone wanted to run truly worst-case simulations of all combinations of IC corners, temperature, supply voltage, discrete cap leakage, ESR, ESL etc etc. You have 2^N simulations. Far too many to do at a transistor level. Seems AMS modeling is your only hope.
Thanks for the input.
- Rob
|