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Worst-case analysis with AMS models (Read 8313 times)
mehregan
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Worst-case analysis with AMS models
Aug 18th, 2008, 6:08am
 
I am looking for opinion from anyone who has experience doing worst-case analysis using Verilog-A/MS and Spectre or AMS Designer.  We would like to parameterize our IC block behavioral models to cover performance over all the different MOS, resistor, temperature, voltage, etc. corners.  Then be able to simulate multiple blocks and discrete components together over all the different possibilities / combinations of worst-case corners.  This may result in many simulations.  

One method is to parameterize the AHDL model with min/max parameters  gathered from transistor level simulation and then use ADE or Spectre's paramset to sweep these parameters in the AHDL model.  However paramset does not work in AMS Designer and ADE carries its own GUI baggage with it.  

Just curious if anyone has tried to model multiple worst-case corners in an AHDL  block model and then tried to tie multiple models together to do many worst-case sweeps in Spectre or AMS?  How did you do the sweeps in AMS if you did not use ADE?  

- Rob
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jbdavid
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Re: Worst-case analysis with AMS models
Reply #1 - Aug 21st, 2008, 11:46pm
 
Thats one of those things that seemed obviously valuable 10 (+?  :-/)  ) years ago when getting started with spectreHDL..

But It turns out really to be the same thing as "corners" at the chip level..
except that at the chip level the worst case conditions are actually statistically nearly impossible..

So we wrapped a monte carlo analysis around spice/spectre to get a better handle on that ..

To make a long story short.. its possible.. Its just that other uses of models have been solving more immediate issues (like design verification) and so this has kinda dropped off the radar screen..

To broaden your case, though I would point out that Worst Case Analysis is really a "Specification Verification" problem..
to prove that the set of specifications I've put on a set of blocks are all
1. Compatible with each other
2. Support the Specifications of the Top Level spec..

Now its something possible to do in Verilog(A/AMS) but the value of using this language (rather than Matlab or SystemC-AMS or Python or putting it in an Excel Spread sheet) is that the models could serve as ready starting point for the top level design verification Testbench development..   If you don't have that follow on need driving you, its probably just easier to do it in Matlab/simulink..

Now there are some of us who could put together a system model in Verilog-AMS faster than in Matlab.... but I bet its just those of us with lots of experience in Verilog and none in matlab.. just my guess.

That's this man's Opinion.. hope it helps..
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jbdavid
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mehregan
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Re: Worst-case analysis with AMS models
Reply #2 - Aug 25th, 2008, 6:17am
 
Yes, if you think about it, worst-case analysis is really a specification verification problem.  If you could do true top-down design and make budgets for all your critical IC and hybrid component parametrics, then you could assure you meet requirements over all worst case conditions .

In more classic bottom up design, corner simulation, monte-carlo and even worst-case types of simulation have been around for many years and are generally accepted.  The problem we see typically is that the IC block is designed by an IC designer with assumptions that other blocks and hybrid discrete components are ideal or at worst nominal.   Even corner simulations are run assuming nominal discrete components, clocks, etc.  

If someone wanted to run truly worst-case simulations of all combinations of IC corners, temperature, supply voltage, discrete cap leakage, ESR, ESL etc etc.  You have 2^N simulations.  Far too many to do at a transistor level.  Seems AMS modeling is your only hope.  

Thanks for the input.  

- Rob
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jbdavid
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Re: Worst-case analysis with AMS models
Reply #3 - Aug 27th, 2008, 1:00am
 
Well Part of the problem falls on the board designer, who uses Pspice rather than SPICE/Spectre/Verilog-A to provide a set of MODEL files for those board level components but rarely with the corners the way the IC designer uses them..
-- after all our Process Design kits have GREAT models for the Silicon resistors caps and all that, but the board level devices come from a different vendor.. and the board level guys always thought that 100K per analog seat was just too much to pay for tools.
so they don't use the same ones... and we wound up talking different languages.
AT the $$ available in the board design space (6K for a years layout license was debated for a day at one startup I was at recently) I just don't see the market for a commercial tool.  you best bets are to leverage one of the math packages or spreadsheets.. or
roll your own tool from Python and XML - and make it an opensource project..   Or see if you can make it work in one of the existing opensource simulator packages like gnucap. or Icarus Verilog..
or SystemC-Ams..
Good luck.
jbd


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jbdavid
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