If you want to simulate a fully-differential amplifier with different input and output common modes in a feedback configuration, simply use a voltage-controlled voltage source (ideal buffer) to connect the output back to the input. You can also use this source to adjust the loop gain in your simulation setup.

Hi there,

Using large resistors in the feedback to close the loop is not a good since they will generate a lot of noise.

What Frank suggested is the right way to do it. Ideal buffers do not add extra noise and allow you to close the loop for different input and output common levels.

Using ac noise analysis will give you a direct noise performance of the amplifier. For such purpose just short the inputs (do not forget to place the input probe in before shorting them) and generate the appropriate common mode level.

The ideal buffer will change the loop gain if its corresponding ac  gain is different from 1. Otherwise the loop gain will be the amplifier´s one.
At the same time, from the DC or bias perspective, the buffer will help you adapt the input and output common mode levels. Again, this will not affect the ac loop gain unless the ac gain for such buffer is different from 1.

Finally, the noise can be integrated to have the overall noise performance for your amplifier. Assuming a one-pole system (or at least having your second pole far away from the dominant one) the noise equivalent bandwidth can be assumed to be ~ 1.57 x the -3dB frequency of your amplifier. So if you integrate such noise up to a very high frequency you should approximate to that number if you meet such conditions.

Hope this helps
Regards

Tosei

Just an other comment:
When you simulate from 1Hz you will also add a lot of flicker noise.
Depending on the application, I think that this very low-frequency
noise is not important.

Cheers

Hi Thomas,

1. I still don't understand why you want to use resistors, vcvs etc. And I don't like to use 1u resistors personally. You can only expect convergence issues with your simulator. Why don't you try simulating the switched-capacitor MDAC stage which is the heart of your pipelined ADC, as it is, i.e. without disturbing its intrinsic configuration. PSS + Pnoise analysis from Spectre (Use timedomain option for sampled systems) would be ideal for this stuff. Anything else you do is simply analyzing another system than what you will have on silicon !!!

Please also read up on using this analysis before you mess with it.

http://www.designers-guide.org/Analysis/sc-filters.pdf

2. You do not need to specify an input voltage source, but since most people calculate input-referred noise, it is helpful to specify it. I got the impression that you were avoiding specifying the input voltage source for noise analysis merely because you did not see how to do it for a differential circuit. Now that you have baluns, that is solved, and you have complete information (input and output noise).

3. You always have to remember that neither your opamps, nor your switches+capacitors have infinite bandwidth. The bandwidth of your opamp probably runs to 10s or 100s of MHz, that of switches+caps to around 100s of MHz. Once you have read up on PSS + Pnoise analysis, and done it a few times, you will realize why you should choose the upper frequency limit for noise wisely.

4. Next time, someone tells you to integrate upto infinity, ask him what his definition of infinity is. As for the upper limit of thermal noise processes, that is given by f0 = (kT/h), where T is temperature, and you can guess the other 2 constants. However, that is only an academic issue. Your real bandwidth is going to be orders of magnitude smaller. Why bother?

5. Flicker noise is an issue as Berti pointed out. You need to choose the lower limit wisely. Usually, for a wideband ADC, it does not matter. The flicker noise at low frequencies may be very high, but the integrated noise power there is usually small (in most cases) compared to the thermal noise in your 10s of MHz bandwidth. Just because your signal is from 2 to 30 MHz does not mean that you can ignore noise at lower bandwidths, unless your final system includes a filter to remove this noise. You may be interested in the band from 2 to 30 MHz, but your circuit does not know that. It will democratically amplify everything it sees in its passband, unless you tell it to pick and choose (place a filter of some kind). I would choose the lower frequency limit based on the longest observation period of interest. That is not a universal choice. Some people will tell you that you need to choose the lower limit based on the longest timeconstant in your circuit, which will usually be limited by leakage. Others will say that you need to choose it depending on the lifetime of the circuit. I don't know the best answer.

Hope that answers your questions.

Regards,
Vivek

OK so I've been sidetracked of late and am now back to looking at the noise of this MDAC stage/amplifier. I agree, I should look at the noise of the entire MDAC stage, including switches and capacitors. I am not so keen, however, on using this pnoise; I read the document and found it a difficult read.
What is the standard way of getting the noise at the output of this MDAC circuit using ac noise analysis?

Is it doing the analysis during both clock phases, then adding the results? I tried this for one phase and the noise was ridiculous; something like 2V.... obviously incorrect.

May I also ask about the transient noise analysis. I take it this would not be suitable; how is this typically used etc?

Thanks for your help on this topic; it's something I can't quite seem to grasp!

I think that transient noise analysis allows large-signal noise simulations.
For a SC circuit such as a MDAC, large-signal noise analysis is probably
not required and  pnoise is faster (more accurate).

Regards