The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 17th, 2024, 11:03am
Pages: 1
Send Topic Print
Strained Silicon (Read 2528 times)
nano_RF
Community Member
***
Offline



Posts: 50
madison
Strained Silicon
Aug 30th, 2008, 11:12am
 
Hi All,

I am not sure if this is the right forum to post this. But nonetheless curious to know about following.

Lets assume that by process manipulation one has got a strained silicon device:-
(1) What could be the possible effect on devices deep-depletion breakdown? If it gets lower then why and vice-versa?
(2) This would be process dependent, but in general would one expect parasitics capacitance to increase?

Thanks in Advance,
Back to top
 
 
View Profile   IP Logged
Berti
Community Fellow
*****
Offline



Posts: 356

Re: Strained Silicon
Reply #1 - Sep 30th, 2008, 7:40am
 
Hi,

The following paper probably answers your question:

C. Claeys et al., "Impact strain engineering on gate stack quality and reliability",
Solid-State Electronics (Pergamon Press), August 2008.

Regards
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.