Hi:
Recently, I need to simulate a capacitance with a second-order voltage input (451.47+4.9*V-0.0143*V^2). For V=sin(1000*t), C=2 pf and a RL=1M ohm, we can get I=RL*d(c*v)/dt, and the pick of the Vout is ≈ 9.8 mV. However, by using spectre, I got different results.

In first approach, I used verilog-a to built a capacitance model.

`include “discipline.vams”

module varactor(p, n);
inout p, n;
electrical p, n;
parameter real c = 2p;
parameter real a0 = 451.47;      
parameter real a1 = 4.9;
parameter real a2 = -0.0143;

real q, v;

analog begin

v = V(p,n);
q = a0+a1*v+a2*pow(v,2);
I(p, n) <+ c*ddt(q);

end
endmodule

This can be compiled in verilog-a, but can not run in spectre.
If I modify the input to 1 order (q = a0+a1*v; since a2 is much smaller than a1), it can run in spectre. However, the pick of Vout is ≈62 mV. Furthermore, if I the RL is increased, the Vout wil  be increased lineraly until 5V (like a saturation phenomenon).

In the second approach, I used an adder (built by verilog-a), a multiplication (built by verilog-a) and voltage sources to synthetize a second-order input in spectre. The synthetized signal is connected to a common capacitance, and also a load resistance is connected to the capacitance in the other side. The simulation result ( in spectre) show that the pick of Vout is ≈60mV. However, simular to  approach 1, as the Rl increasing, the Vout is increasing until 5 V and saturated.

Could someone tell me
1. Why the simulation result is 60 mV but not 9.8 mV ?
2. Why did the "saturation phenomenon" occur ?
3. How to built a second-order input capacitance that can be used in spectre (approach 1 ) ?    

Thnaks a lot.

Dear Geoffrey:

Thanks a lot for your reply  :)


ChinFu