Hi Trashbox,

Be careful!...if you are going to chop the BG reference be aware the amplifier is not the only and (eventually) not the main source of offset in the circuit.
If you get offset in the bipolars used for building up the delta VBE that will generate a lot of offset (the offset current you'll get will be proportional to the e^Voff. Therefore you might want to think about chopping the bipolar translinear loop too.

Regards
Tosei

trashbox wrote on Sep 7^th, 2008, 11:47pm:


Statistical Analysis and Optimization of a Bandgap Reference for VLSI Applications
J ¨ URGEN OEHM1 AND ULRICH GR ¨ UNEBAUM2
1Infineon AG, D¨usseldorf, Germany
2ZKOM GmbH, Dortmund, Germany
E-mail: J.Oehm@infineon.com; Grueneba@zkom.de
Received February 15, 2001; Revised February 27, 2001; Accepted February 27, 2001
Abstract. Voltage and current references are widely needed for all kinds of integrated circuits, as most applications
require temperature-independent references with a high reproducibility in mass production. For this purpose
normally bandgap references are used. Though it is a common task to set up an application specific bandgap circuit,
handling of the statistical design aspects is often not a standardized step in the design flow. This article describes
some of the steps that were taken during the design of a bandgap reference for a given VLSI application. All
statistical simulations were carried out with the simulation tool GAME (General Analysis of Mismatch Effects)
which is used at Infineon/D¨usseldorf since 1999.
Key Words: bandgap, statistical analysis, mismatch, optimization, simulation

trashbox wrote on Sep 7^th, 2008, 11:47pm:


This is probably too late to help you, but maybe someone else... The importance depends on your process variations and the design topology you use. Generally you want to make the ΔV_BE as large as possible. This reduces the ratio of the gain resistance which lowers the sensitivity to everything (and also lowers the noise). Not much you can do beyond that for topology except chopping.

Once you decide on a topology there is a method to optimize the areas allocated to each device. I did a paper that might help you optimize (CICC 2004): http://web.engr.oregonstate.edu/~gregoire/papers/CICC2004.pdf . The resulting bandgap had a σ of 2mV. The paper also presents a substrate PNP Darlington topology that doubles the ΔV_BE.

One thing you should do is make the area of the gain resistors equal by using a parallel/series structure. For example, for a 9:1 ratio you would use 3 Rs in series for the big resistor and 3 Rs in parallel for the small resistor. This method reduces the area considerably because resistor mismatch of this gain circuit is generally the highest mismatch contributor.

rg

HdrChopper wrote on Sep 8^th, 2008, 6:25pm:


sorry to dig up an old post, because i happened to have a wondering on the same topic.

as Tosei pointed out, sometimes the main error source is not from the opamp. but in such cases, how are we supposed to chop, for example, the bipolar loop? it is not a fully differential loop, which is the basic requirement to apply a chopping scheme.