Hi all,

I am trying to do a co-simulation of my control logic for my ADC.
I want to verify my Flow. i am new to mix simulation.

I wrote a vhdl code for my control-logic and got a gate-level verilog.Netlist of my design, using standard-cell '.lib' or '.db' format.
And now i am trying to parse this Netlist through ' verilogin '. and would be simulation with the other analog parts of my ADC.

The 'Reference Library' in verilogin? is this the same standard-cell '.db'\'.lib' file? because when i tried to define this in cds.lib, i find no cells in the ' Library Manager '. is this Ok?

Even though I discard this and try parsing the Netlist. i get some errors:

VerilogIn: *W,31 => Module X in FSM_file  not defined.Module FSM_file will be imported as functional.

VerilogIn: *W,101 => Could not find symbol master for instance
XY .Functional view won't have this instance.


Please Help me ..

Thanks........

Hi  bernd / all,

Thanks for your reply.
I guess i solved it

1. Reference Library "CDK"

2. -V option i provided the link of the standard-cell file in verilog format. ".V"


I found few errors, mentioning the verilog
" Verilog definition for module AND2 was not found. Using lib 'techlib' cell 'AND2' view 'symbol' as its symbol.

But i guess I could discard this.


Thanks a lot Again

cheers
dinac