The argument that the PSD of the SDM output does not show spurious but the closed PLL is the following:
If the PLL in time continous phase domain with linear behaviour get a SDM number distribution without spurs the closed loop should also be spurious free!
But the model of operating the PLL in phase domain is not true:
1. The frequency step, which is a ramp in phase domain is applied somewhere within the phase cycle. That lead to memory effects where the cycle period time depend on previous times.
2. The frequency step is no addition of a phase ramp to the loop input. Instead the loop gain change too.
Both effects are typical neglated because these does not fit into a linear time continious PLL model. A simulation is the way to work with. I think Ian Galton describe in an article the differencies.
http://ispg.ucsd.edu/pubs/Wang_ISSCC2008_slides.pdfHope that helps. Dither was also a small piece to improve.