hugh
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Hi all,
I'm designing a PLL and using the tsmc 0.13G process. But the gate leakage current is about 1nA/um^2 for NMOS. So when using nmos as capacitors what should I do?
Another question is the Ioff is also high, 500pA for NMOS of 10/0.13. So the power down current for a large scale digital circuit is also very high, I guess about 100uA for about 200K gates. How to solve this?
Some suggest to use the 0.13 LP process. However I heard the leakage current is more severe in 90nm, and since we will migrate to 90nm later, I think we'd better solve it now.
Thanks for any suggestions,
Hugh
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