In just about every SAR, Delta-Sigma converter, and other switched cap circuits, the summing junction (SJ) plate of the capacitors are always shielded from the top of the chip.  With poly-poly caps, this was easy since you could use whatever metal layer you wanted.  With MIM caps, it now looks like the bottom plate of the cap, i.e. the plate that sees the parasitic to substrate, is used for the sensitive SJ nodes since the top plate is shorted to top metal above which is effectively a shield.  I'm assuming that the MIM cap must be made on the second highest level of metal with the capacitor top metal (CTM) sitting above that with vias up to top metal.

First off, why shielding a necessity?  Is it to protect from piezo-electric effects?  Is it to absorb EMF before it disrupts the SJ nodes?  Is there some other reason?

With many switched cap designs using poly caps, I have seen them split the cap into two and arrange them back-to-back.  This has a number of positive effects, not the least of which is eliminating the linear term contribution of the voltage coefficient of those caps.  What can be done when using MIM caps that cannot be placed on arbitrary metal layers, i.e. fixed to the second highest metal line?  Can we no longer place these caps back-to-back?  If not, are there any other ways to compensate for the linear voltco?

I know that we will have to be very careful with the layout for all horizontal and some vertical routes, but my question is slightly different.  I am specifically asking about the need to shield the SJ nodes from above, not from any internal signals but from the outside world.  

For example, if the SJ node is on the CTM layer with top metal above it, does this suffer more from package stresses than if the cap were flipped?  Is there some other reason to not expose some critical node when looking from above?  EMF, maybe?

Adam

I would not have thought that matching would be affected in more modern processes that planarize the back end.  Have you ever seen data comparing mismatch between shielded and unshielded caps in processes using CMP?

I have not seen any data, but in a planar process, edge effects should be negligible.  I remember when working in non-planar processes, they gave us rules of thumb for the distance from caps and resistors that needed to match and everything else.  They always requested a larger separation when we did want things to match.  

Of course, all of this would not necessary help between dense and sparse layouts.  I know there can be differences in matching there due to lithography and etching.  I've seen concrete evidence that there are differences but nothing to say one is always better than the other.