I'm design a large output current linear LDO with pMOS as pass element and want to save area by using small W/L pMOS.

Is there any method to decrease pMOS Vth? Thanks!

Trashbox

Hi,

You could try biasing the body of the pass transitor about 200mv below the supply voltage.

What is the min drop out you need for you app? Depending on the drop out the pass transistor migth not need to be super large. You could eventually allow the pass transistor to enter into triode region without major consequences since usually the pass transistor stage does not gain too much, even when working in sat region (since usually the load is very small to achieve large gains).

Hope this helps
Tosei

hi tosei,
           i have a question regarding u r ans. from gain point of view it doesn't matter whether pass transistor is working in sat or triode(as you said,provided ldo is heavyly loaded),but from supply noise point of view if it is triode it will pass most of the noise to output. correct me if i  ma wrong.
hi trashbox,
                   the following paper might help you,they have  implemented same idea(more or less using body terminal,but its prone to forward biasing)

36 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998
A Low-Voltage, Low Quiescent Current,Low Drop-Out Regulator
Gabriel A. Rincon-Mora, Member, IEEE, and Phillip E. Allen, Fellow, IEEE

hi tosie,
           thanks for your answer.can please tell me is there any advantage of pass transistor in triode apart from low drop(may be i guess stability may improve).can you give any reference based on this?
Thank you.

Possible way to decrease the threshold voltage is to connect the bulk to the gate. This is so the called DTMOS device (Dynamic Threshold MOS). You have to be careful with the operating point of such device, because the bulk is slightly forward biased.

Regards,
PalmRunner