Tlaloc
Community Member
![* *](https://designers-guide.org/forum/Templates/Forum/default/stargold.gif) ![* *](https://designers-guide.org/forum/Templates/Forum/default/stargold.gif)
Offline
Posts: 81
Dallas, TX
|
The only problem with tying the reset pin to ground is simulation. If you are trying to run this in verilog, you will always get X at the output. In real life, however, the flops will start at one of the four states in an indeterminate manner, but the output is well behaved so long as you don't care about the initial condition.
|