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sunnylvee

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san jose

Who should be the chip level verification engineer(digital+analog chip)?
Dec 18^th, 2008, 2:05pm

As we all know, verification is taking 80% of the design effort and is becoming more critical as designs become more complex. Common functional errors like the chip not powering up, flipped buses, etc. happen in complex designs when there is not a comprehensive verification method.

Analog/Mixed signal designers have realized this problem (http://www.edadesignline.com/howto/211600976) and the EDA companies have tried different methods to improve this situation (http://www.edn.com/article/CA6426885.html).Here I�d like to discuss who should be the chip level verification engineer: a digital verification engineer, an analog verification engineer* or system design verification engineer?

As an analog verification engineer, I have done functional SOC verification for chips at the chip and block level and have always found bugs before tape-outs. I believe that the analog verification is the diamond of SOC verification. But I know that there will be other opinions about our methodology (http://www.designers-guide.com/approach.html).

I hope to get different opinions from all of you. Anyone interested in this topic can email me and we can talk more about this.

Sunny

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jbdavid

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Re: Who should be the chip level verification engineer(digital+analog chip)?
Reply #1 - Dec 18^th, 2008, 7:05pm

I find VERY Few Analog "Design Verification" engineers that know much about STANDARD verification practices like Planning and functional Coverage.

I find very few Digital "Design Verification" engineers that understand the functionality of Analog Circuits, or know the Analog Languages For Writing models (because model based simulation is IMHO a requirement, except for simple analog blocks where faster spice engines can help, and few of the faster spice engines support the TESTS that have to be writting in the mixed signal language..

I think you Need BOTH people teaming up to get the job done right!!!

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jbdavid
Mixed Signal Design Verification

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sheldon

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Re: Who should be the chip level verification engineer(digital+analog chip)?
Reply #2 - Dec 20^th, 2008, 3:59am

Jonathan,

� Do you think that it is possible to encapsulate analog blocks inside
the digital circuitry and only test the system with digital stimulus, that
is with the digital coverage-driven verification methodology? For
example in high speed I/O design, you can use loopback to test the
system. In loopback mode, the inputs and the outputs are digital.
The types of errors that Sunnylvee is describing are functional and
connectivity errors would seem to be consistent with this strategy.
Or are real systems to complex to use this type of approach for
verification?

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Sheldon

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Peruzzi

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Re: Who should be the chip level verification engineer(digital+analog chip)?
Reply #3 - Jan 2^nd, 2009, 9:34am

My answer: Someone who is strong in both
1. Analog, Digital and Mixed-Signal circuits and systems and
2. Digital Verification
and it doesn't matter which was learned first. The lead chip verification engineer must get beyond labeling himself or herself as having either an analog or a digital orientation.

Fact: Digital verification is a mature process and the field has lots of experts. Someone with only analog verification experience can't hope to just wing it with the well established suite of digital verification tools.

Fact: Analog verification requires sensitivity to the nuances of analog reality.
If analog and digital are closely coupled, for instance an automatic gain control loop controlled by digital feedback from after the A/D converter, then verification leadership calls for analog knowledge and sensitivity to analog non-idealities. In this AGC loop example, it's likely there is a significant delay within the VGA between the the time digital feedback programs a new gain setting and the time the new gain is established at the VGA output. A naive AMS model not taking this delay into account could hide a system-level algorithmic error in which the updated VGA output is sampled too quickly after programming.

One question: Which is easier, for an AMS Verification engineer to learn the digital verification process or for a Digital Verification engineer to gain analog expertise?

Another question: How does an AMS Verification engineer teach him or herself to come up to speed with the suite of digital verification tools? Which tools, books, tutorials in which order?

I've heard Xuropa.com has some "playgrounds" where one may try out and learn design verification tools. �Has anyone tried it out?

Best regards,

Bob P.

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ywguo

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Re: Who should be the chip level verification engineer(digital+analog chip)?
Reply #4 - Jan 24^th, 2009, 6:34am

Can we replace all the analog blocks with behaviour models, Verilog-A model or Verilog-AMS model? Can we extend the digital verification method to a mixed-signal verification method?

Though the behaviour model often neglects some analog realities, it perhaps reduce the verification speed dramatically. At least the accuracy of the analog block is not critical when we very the function of SOC.

If this method is available, feasible, I'd like to appoint a digital verification engineer for the chip level verifcation.

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jbdavid

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Re: Who should be the chip level verification engineer(digital+analog chip)?
Reply #5 - Mar 19^th, 2009, 10:34am

There are many questions here..
Using Behavioral models to accelerate sims is the proven methodology I've been doing for over 10 years. I'll claim that, while there is a learning curve to this, there is a reservoir of experience in the industry that can support this.

Some teams, for some design types, have successfully used digital verification (simulation based) techniques including the use of SystemVerilog testbenches and assertions to capture design coverage. there are even libraries of verification IP available that will let you use a coverage approach on some analog quantities.

In my opinion, anyone want to work in this space will find study of both Digital verification techniques, and analog behavioral modeling techniques of a lot of value.

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jbdavid
Mixed Signal Design Verification

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love_analog

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Re: Who should be the chip level verification engineer(digital+analog chip)?
Reply #6 - Apr 23^rd, 2010, 7:01am

My response to Sheldon (in particular)

In a big SoC, we have found that modeling analog in a pure rtl is the only way to go. Yes, the level of abstraction will miss key points (such as closed loop PLL locking, bias connectivity etc). So, a very clear communication between analog designer and RTL engineer is essential.

In general, i believe my response will differ from people who may not have large digital content (by large I mean a GPU, CPU kind of level of complexity). In that case capturing analog through verilogAMS etc will provide a greater degree of accuracy.

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loveanalog.blogspot.com
The Power of Analog

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jbdavid

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Re: Who should be the chip level verification engineer(digital+analog chip)?
Reply #7 - Nov 10^th, 2010, 11:52pm

Sheldon,
to answer your question directly, I don't yet do any chips where all the signals at the pins are digital, so no, for the analog pins you need "real number modeling" a la wreal (verilog ams) or wire real (icarus verilog extension to 1394 verilog) or vhdl real (or record of reals) signal types.

but only those signal paths would involve real number modeling, all the digital blocks would be c, rtl, or gate level digital (sometimes with annotated sdf and runnign timing checks)

But even with real number modeling at the pins you should be looking at code coverage, and writing your tests so that you can collect test/feature coverage data as well.

if the design is small enough, and you pay for the fast simulators, you might be able to leave parts of a pll design at the transistor level, but I'd run a lot less tests with this type of configuration than with the models.
Jonathan

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jbdavid
Mixed Signal Design Verification

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Nimrod Ben-Ari

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Re: Who should be the chip level verification engineer(digital+analog chip)?
Reply #8 - Aug 28^th, 2011, 12:39am

Hi,
as an Analog engineer I did Full-Chip verfications on several chips.
I think that using behavioral models is a risky solution as they are only as good as you wrote them - there would always be some combination that would pass on the behavioral model but that the analog block would crush.

on the other hand you can't check chip functionality using analog simulator as even FastSpice simulators would take a couple of days to go through a few uSec.

the best solution, from my point of view, is to verify the Digital circuits functionality using behavioral models, and Analog blocks with FastSpice tools for the TO clearance.

Nimrod

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Who should be the chip level verification engineer(digital+analog chip)? Reply #9 - Oct 27^th, 2011, 5:02pm http://www.edn.com/article/459775-Efficient_simulation_and_validation_for_mixed_... give it a read... A lot of places do full up digital verilog end to end with a digital definition of the mixed signal devices. Sort of pseudo analog.
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged