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Linter for VHDL-AMS, Verilog-AMS (Read 36 times)
hakke
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Linter for VHDL-AMS, Verilog-AMS
Sep 05th, 2011, 3:22am
 
Hi!

Is there a linting tool for analog design blocks? We have mixed signal designs where the top level is analog. For RTL we use SpyGlass to do static code analysis. But due to presynthesis, this tool does'nt work with behavioral code. So, is there a similiar tool for analog designs?

BR,
hakke
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