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Nimrod Ben-Ari New Member Offline Posts: 9 Israel	clock generating Dec 21^st, 2008, 6:27am Hi, I have a very accurate rising edge signal at ~100MHz, I need to generate a 50% duty cycle output at the same frequency. could any one suggest a way for implementing such a circuit? Thanks, Nimrod Ben-Ari
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ywguo

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Re: clock generating
Reply #1 - Dec 24^th, 2008, 7:16am

How much tolerance for the duty cycle? �%1 or �5% ???

If you need very accurate 50% duty cycle, you'd better generate it out of a PLL or a DLL because they have very precise delays or phases.

If very accurate 50% duty cycle is not a need, a long inverter chain is a good replacement because it is simple, power saving, and of small area. The ~100 MHz clock is fed to the inverter chain, while it is sampled by the output of each inverter. Suppose one inverter has one unit delay, then it is easy to determine how much unit delay that one clock cycle is equal to. If one cycle is equal to 2N unit delay, the required signal of 50% duty cycle is made out of the outputs of the Nth inverter and the 2Nth inverter.

Yawei

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loose-electron

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Re: clock generating
Reply #2 - Dec 25^th, 2008, 6:59pm

Agree that the PLL/DLL is the most accurate way of doing this.

Another method is an integrator (I into C) and some holding capacitors - Integrate over the period, hold the voltage value of the integration, do 50% voltage division and compare that to the nexct integration cycle. At the 50% of the integration amplitude point flip the state of the clock over.

With a little thought this can be done where all the delays, mismatches and offsets are cancelled out.

The string of inverters sounds interesting, but at 100MHz thats probably a whole lot of inverters, and if you want good accuracy, needs to be updated for PVT variances that are ongoing. Power and temperature are going to be changing all the time.

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Jerry Twomey
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Nimrod Ben-Ari New Member Offline Posts: 9 Israel	Re: clock generating Reply #3 - Dec 27^th, 2008, 10:07pm thanks to all the replies. I found a third way to do this, I'm using a XOR circuit at the input of the clock block to double the in coming frequency and then I'll divide it at the output using TFF, getting a 50% DC with the correct frequency.
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: clock generating Reply #4 - Dec 28^th, 2008, 6:08pm Hi Nimrod, I doubt that the third way, the XOR method, is not feasible. Would you please depict the schematic here? How do you simulate? Do you simulate with a clock input of 50% duty cycle? Yawei
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Nimrod Ben-Ari New Member Offline Posts: 9 Israel	Re: clock generating Reply #5 - Dec 28^th, 2008, 9:49pm Hi Yawei, I use the XOR at the input of the a sort of DLL that reduce the Jitter, the problem was that to get a 50% duty cycle at the output I had to divide the output clock by two. by adding the XOR at the input I was able to get the orginal frequency with the desired duty cycle. Nimrod
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