neoflash
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Mixed-Signal Designer
Posts: 397
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Assume we are designing a CMOS DDR3 driver, user requested different output driver impedance to cover different capacitive loading.
For example, 18 DRAM units may require 20ohm output impedance while 36 units may require 12ohm output impedance.
I'm curious that if whether we should use a faster slew rate for heavy capacitive loading, or use a slower slew rate?
Fast edge rate will incur more reflection, any consideration on this effect? Please recommend some literature if any, thanks.
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