The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Aug 14th, 2022, 2:32am
Pages: 1
Send Topic Print
How to predict the DNL graph in Pipelined ADC (Read 11590 times)
prince_123
New Member
*
Offline



Posts: 3

How to predict the DNL graph in Pipelined ADC
Jan 04th, 2009, 10:04pm
 
Dear All

DNL - (Differential Non linearity) is characteristic of any data converter.

I would like to know how to predict DNL graph in pipelined ADC when you have


1. Only gain error in OTA, all other components are ideal.

2. Offset error in flash comparators and all other components are ideal.

3. How is the choice of Vref (Reference voltage) affects the final DNL graph.


If some one can explain it in an intuitive way, it will be of great help to understand pipeline ADC better.


Regards prince
Back to top
 
 
View Profile   IP Logged
vivkr
Community Fellow
*****
Offline



Posts: 780

Re: How to predict the DNL graph in Pipelined ADC
Reply #1 - Jan 5th, 2009, 3:27am
 
prince_123 wrote on Jan 4th, 2009, 10:04pm:
Dear All

DNL - (Differential Non linearity) is characteristic of any data converter.

I would like to know how to predict DNL graph in pipelined ADC when you have


1. Only gain error in OTA, all other components are ideal.

2. Offset error in flash comparators and all other components are ideal.

3. How is the choice of Vref (Reference voltage) affects the final DNL graph.


If some one can explain it in an intuitive way, it will be of great help to understand pipeline ADC better.


Regards prince


Hi,

That is not at all any easy question to answer, especially posting onto a forum. Let me try to answer one part (effect of finite opamp gain), and you can extend the same to other nonidealities:

Assume the simplest pipeline ADC (1.5b stage) with a gain of 2. This has a piecewise linear characteristic with a slope of exactly 2 V/V and discontinuity at the thresholds of the 2 comparators, at +Vr/4 and -Vr/4, if we denote the full signal range as spanning from -Vr to +Vr, where Vr is the reference voltage.

Finite gain in the opamp will mean that the slope will be slightly less than 2 V/V, more precisely, it will be approx. 2 (1-Adc). Ideally, the discontinuity at each comparator threshold would have had a step height of exactly Vr, but now this shrinks by approx. 2*Vr/Adc. This is the DNL of your pipeline stage due to finite opamp gain.

Anything which changes the slope of the gain curve will cause DNL in the same manner, because your digital postprocessing of the bits from each stage assumes that the gain is 2 V/V.

Comparator offsets in the 1.5 b/stage scheme will only cause the thresholds to move around, but as long as the movement is smaller than +/-Vr/4, this should be OK as the stage output does not exceed the limits (-Vr,+Vr).

Regards,

Vivek

P.S. I might have a factor of 2 missing somwhere in my expressions. Just write out the expressions once to be sure that you have it all correct.



Back to top
 
 
View Profile   IP Logged
sheldon
Community Fellow
*****
Offline



Posts: 751

Re: How to predict the DNL graph in Pipelined ADC
Reply #2 - Jan 5th, 2009, 11:49pm
 
Prince,

  You might want to look into the literature to verify the following. My
understanding is that as long as the gain error is less than the bit
overlap correction range it will have no little on the DNL of the ADC.
The bit overlap correction should compensate for the error. The
limitation of bit overlap correction is that the error due to the dac
can not be corrected. So unless the DAC capacitors values are
mismatched, the only DNL you will be seeing is due to numerical
noise in the simulation. You can find some discussion of the error
sources at the following link

http://www.eecg.utoronto.ca/~kphang/papers/2002/rfung_AccuracyXofXADCs.pdf

NOTE: bit overlap correction == digital correction in the reference

You can also find some information at the following link,

http://www.scribd.com/doc/7221467/abothesis
see pages 90-98

                                                            Best Regards,

                                                               Sheldon

Back to top
 
 
View Profile   IP Logged
prince_123
New Member
*
Offline



Posts: 3

Re: How to predict the DNL graph in Pipelined ADC
Reply #3 - Jan 6th, 2009, 3:30am
 
Thanks  Vivek and Sheldon  :)

I have understood the following things

1. Because of the OTA gain error, the output can only swing from -vref + vref/AB to vref - vref/AB for the next stage

2. This small swing at the extreme causes small digital steps which shows as negative DNL.

3. Positive DNL is caused because of the gain error of the previous stage, the residue has to be 1/AB times more to cause the digital code to change. This makes the digital step wider that what it should be.

4.  Negative DNL is used as a spec to find the open loop OTA gain required.

Please correct me if I am wrong.
Back to top
 
 
View Profile   IP Logged
sheldon
Community Fellow
*****
Offline



Posts: 751

Re: How to predict the DNL graph in Pipelined ADC
Reply #4 - Jan 6th, 2009, 4:24am
 
Prince,

  Sorry, did more digging and found this reference. It even
includes some of the plots you are looking to generate Avo
vs. DNL. Enjoy!

                                                      Best Regards,

                                                        Sheldon

http://www.beingblue.com/math/Circuits/ppln_adc/080512%20Design%20of%20a%20Pipel...
Back to top
 
 
View Profile   IP Logged
sheldon
Community Fellow
*****
Offline



Posts: 751

Re: How to predict the DNL graph in Pipelined ADC
Reply #5 - Jan 6th, 2009, 4:32am
 
Prince,

  This Design Review report that includes the
relationship between open loop gain and DNL.

http://huangkejie.com--out-of-date/Documents/A%201.5V%2010-bit%2020MHz%20CMOS%20...


                                                        Best Regards,

                                                            Sheldon
Back to top
 
« Last Edit: Sep 7th, 2011, 6:16pm by Forum Administrator »  
View Profile   IP Logged
prince_123
New Member
*
Offline



Posts: 3

Re: How to predict the DNL graph in Pipelined ADC
Reply #6 - Jan 6th, 2009, 8:21am
 
Thanks a lot Sheldon

I was looking for information like this in pipeline ADC. It will definitely help me with the design.

Back to top
 
 
View Profile   IP Logged
vivkr
Community Fellow
*****
Offline



Posts: 780

Re: How to predict the DNL graph in Pipelined ADC
Reply #7 - Jan 6th, 2009, 11:37pm
 
prince_123 wrote on Jan 6th, 2009, 3:30am:
Thanks  Vivek and Sheldon  :)

I have understood the following things

1. Because of the OTA gain error, the output can only swing from -vref + vref/AB to vref - vref/AB for the next stage

2. This small swing at the extreme causes small digital steps which shows as negative DNL.

3. Positive DNL is caused because of the gain error of the previous stage, the residue has to be 1/AB times more to cause the digital code to change. This makes the digital step wider that what it should be.

4.  Negative DNL is used as a spec to find the open loop OTA gain required.

Please correct me if I am wrong.


Hi Prince,

I was not referring to the reduced swing at the extremes of the signal range +Vr and -Vr, but the change in the height of the transition between 2 adjacent piecewise-linear segments at each comparator threshold. I think this is much more severe.

These are normally described well in most papers on the subject, but unfortunately, I don't see them in the 2 links attached in Sheldon's post.

Regards,

Vivek
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2022 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.