Hi all,

I'm completely new to mixed signal design, and i have a couple of questions about this SHA. The opamps were implemented using single stage differential pairs with current mirror loads.

1) When I simulate this circuit without compensation, it is unstable. However, the best place I can see to stabilize the circuit is exactly where C_HOLD is. If I increase C_HOLD, i assume it will affect the maximum sampling rate...Any suggestions?

2) This is related to (1)...how do we decide the value of C_HOLD? I guess it is related to the number of bits required. So a cap accumulates noise equal to kT/C right? Assume 1pF, then kT/C=4nV². Therefore LSB/2 = 0.063mV and maximum no of bits for full scale of 1 V = 13 bits. Does that sound right?

3) Assuming the op amps are infinitely fast, is it correct to say that the sampling rate here is limited by the R of the switches and C_HOLD?


Lastly, as i'm completely new to this, I would appreciate any suggestions on how to start on on this huge topic (ADC design). I figured I would read up on SHAs then move on to comparators...Any useful references would be great too.


thanks,
Aaron

Thanks for the reply,


I'm actually got this circuit from Johns & Martin. Very good book.

btw, since the OTA determines the speed of the circuit, how would I calculate the maximum sampling rate based on the OTA speed? As a rough calculation I'm thinking if i want 9 bit accuracy, then i need to wait around 7 time constants. So if my unity gain frequency is 1 GHz, then the maximum sampling rate based on the small signal bandwidth would be 142 MSamples/s. Does that sound right?

For the gain, I'm thinking that the accuracy of the amp is going to be equal to 1/LG where LG is the loop gain. So for 9 bit accuracy (approximately 0.1% for 0.5LSB), I need a gain of at least 1000 (60 dB). Does the amp need to have 60 dB gain all the way up to the input frequency, or just at DC? I guess it is just DC since it would be pretty impossible to have a 60 dB gain up to input frequencies of 100 MHz...


thanks,
Aaron

Hi Vivek,


thanks for the advice...Actually at the moment I'm totally new to SHA design, so i'm just doing a bit of a survey of my options. I have since been trying a design more similar to the one you're talking about. I'm actually having a bit of trouble finding information on how to simulate the SHA properly. I'll have another look at the spectreRF manual, but if you know of any better resources, it would be very helpful,


thanks,
Aaron

Hi Aaron,

PSS analysis and co. are of course indispensable for simulating S&H type of circuits.

Typically, the "switch" (everything except the sampling cap) limits the THD. You can simulate THD with transient analysis and strobing. qpss is supposed to be very good here although I have not really used it.

If you are starting out in the area, you might want to look at the following references;

1. JSSC paper by Dessouky & Kaiser (I think it is Mar. 2001 but I don't know anymore, there is only one JSSC paper with these 2 guys). Describes a good bootstrapped switch and has references to other papers with the same stuff.

2. Ph.D. thesis of Mikko Waltari (U. Helsinki): The thesis is available online (google it) and has a wealth of detail about sample-and-holds in one of its chapters.

If you cannot find any of these, just send me post a reply here and I will hunt down the complete citation and online links to send to you.

Regards,

Vivek

Hi all,


thanks for all the help. I just read the sc-filter simulation document and it was very helpful. I'm also familiar with the bootstrapped switch. I'll see if I can find the thesis Vivek was talking about. I'm more or less familiar with the PSS and PAC analysis ...

Some things i'm not too sure about...

I'm interested in using the SHA for an ADC, so should i add an ideal sample and hold to the output of the SHA? I think what i have is actually a track and hold amplifier...


thanks,
Aaron

EDIT: I removed my other question cos i found out what strobing is here

http://www.designers-guide.org/Forum/YaBB.pl?num=1118555245

Hi Yawei,


its actually based on Fig. 8.10. Instead of tying the positive terminal to ground, an additional switch is connected which should inject an equal amount of charge as the main switch as the SHA goes into hold mode. This is supposed to reduce the hold step.

As for the ideal S/H, i'm not really sure. In the sc-filter document on this website, an ideal S/H was added to the output of the track and hold. In my case, i eventually want to use the S/H for ADC design. I'm not sure, but if this S/H is connected to a clocked comparator, then I suppose the output i'm looking for is S/H, not T/H...please correct me if i'm wrong.

btw adding an ideal S/H appears to be the same as strobing the output in transient. Is that right? If so, how would I get the same effect in PSS analysis without adding an ideal S/H? Last question (for now ), I read that strobing is done to avoid the interpolation error in the DFT. Could someone please elaborate a bit on that?

thanks,
Aaron

EDIT:

A couple more questions if its not too troublesome...
1. I ran PSS and PAC to find the SHA gain, and found that the -3dB BW is not too dependent on the sampling frequency. Seems like this is a result of the switch being able to switch much faster than the op amp can settle. Does that sound correct?

2. What is the small signal BW? My design has a -3dB BW of around 20 MHz (from PAC analysis), but if i want to use it for a 9-bit accuracy (1/2LSB = 1mV = -0.009 dB), the BW is only 100 kHz. Does that mean my maximum input frequency is 100 kHz for 9-bit accuracy?  

btw i'm now simulating a different SHA which is faster (Fig. 8.13, Johns & Martin)

thanks,
Aaron

aaron_do wrote on Jan 12^th, 2009, 5:08pm:


Yes! you would ideally need an S/H and not a T/H, but you can probably not build anything like that. So, one usually uses a T/H to take an input sample for processing in the pipelined ADC, and the comparators of the first stage usually need to be quite fast to
track the continuously varying input. Depending on your design requirements, you can perform several tricks. You would need to read up some papers on this. Try that thesis by Waltari from HUT Finland. Papers on JSSC by

Scott Bardsley et. al. (Sep. '06)
Gulati et. al. (Aug. '06)
These refs deal more with circuit techniques. If you want basics on pipelined ADCs, try the theses of Andy Abo, David Cline etc. on kabuki.eecs.berkeley.edu.

Quote:


Yes! strobing is like adding an ideal S/H but is only an option in transient analysis and it only forces the simulator to explicitly compute the state of your circuit at the point of interest and output the result. PSS could probably not use something like this and would need an explicit S/H (exception Pnoise analysis with option timedomain).

By computing the state of the circuit exactly at uniformly spaced time instants, you make the job of the DFT easier, else the simulator will interpolate the desired state of the system from adjacent points which can cause considerable error in the DFT, especially for high DR systems.


Quote:


Depends on whether your switch has linear Ron or nonlinear Ron (vs. input voltage), and if you can live with some gain error in case your switch has more or less linear Ron. Mostly, the THD introduced by the switch will be the criteria.

Regards,

Vivek

Quote:

aaron_do wrote on Jan 12^th, 2009, 5:08pm:

I don't have my copy in front of me, but the schematic still doesn't look right.  The way that you have it, there is no way for you to set DC on the pos terminal of amp2.

Quote:

I agree with Vivek's main point, but I don't think that sources with a S/H will give the same answer as timedomain in Pnoise.

http://www.designers-guide.org/Forum/YaBB.pl?num=1220976977/2#2

Quote:

Aaron,
You just need the 60dB at DC.  To be more accurate, you need your loop gain to be 60dB, not just the open loop gain of the amp.  Also, the important number for settling is where the loop gain crosses 0dB, not the open loop gain of the amp.  So, if there is gain due to the feedback, you need higher bandwidth.  I know for T/H circuits, the gain is normally 1, but this is something to always keep in mind.

Adam