aaron_do wrote on Jan 12th, 2009, 5:08pm:Hi Yawei,
As for the ideal S/H, i'm not really sure. In the sc-filter document on this website, an ideal S/H was added to the output of the track and hold. In my case, i eventually want to use the S/H for ADC design. I'm not sure, but if this S/H is connected to a clocked comparator, then I suppose the output i'm looking for is S/H, not T/H...please correct me if i'm wrong.
Yes! you would ideally need an S/H and not a T/H, but you can probably not build anything like that. So, one usually uses a T/H to take an input sample for processing in the pipelined ADC, and the comparators of the first stage usually need to be quite fast to
track the continuously varying input. Depending on your design requirements, you can perform several tricks. You would need to read up some papers on this. Try that thesis by Waltari from HUT Finland. Papers on JSSC by
Scott Bardsley et. al. (Sep. '06)
Gulati et. al. (Aug. '06)
These refs deal more with circuit techniques. If you want basics on pipelined ADCs, try the theses of Andy Abo, David Cline etc. on kabuki.eecs.berkeley.edu.
Quote:btw adding an ideal S/H appears to be the same as strobing the output in transient. Is that right? If so, how would I get the same effect in PSS analysis without adding an ideal S/H? Last question (for now
), I read that strobing is done to avoid the interpolation error in the DFT. Could someone please elaborate a bit on that?
Yes! strobing is like adding an ideal S/H but is only an option in transient analysis and it only forces the simulator to explicitly compute the state of your circuit at the point of interest and output the result. PSS could probably not use something like this and would need an explicit S/H (exception Pnoise analysis with option timedomain).
By computing the state of the circuit exactly at uniformly spaced time instants, you make the job of the DFT easier, else the simulator will interpolate the desired state of the system from adjacent points which can cause considerable error in the DFT, especially for high DR systems.
Quote:thanks,
Aaron
EDIT:
A couple more questions if its not too troublesome...
1. I ran PSS and PAC to find the SHA gain, and found that the -3dB BW is not too dependent on the sampling frequency. Seems like this is a result of the switch being able to switch much faster than the op amp can settle. Does that sound correct?
2. What is the small signal BW? My design has a -3dB BW of around 20 MHz (from PAC analysis), but if i want to use it for a 9-bit accuracy (1/2LSB = 1mV = -0.009 dB), the BW is only 100 kHz. Does that mean my maximum input frequency is 100 kHz for 9-bit accuracy?
Depends on whether your switch has linear Ron or nonlinear Ron (vs. input voltage), and if you can live with some gain error in case your switch has more or less linear Ron. Mostly, the THD introduced by the switch will be the criteria.
Regards,
Vivek
Quote:btw i'm now simulating a different SHA which is faster (Fig. 8.13, Johns & Martin)
thanks,
Aaron