I have a problem when trying to run analog simulations in ams designer on circuits that contain digital cells that use inherited connections (we would like to simulate the transistor level for the digital cells, not the verilog).

It seems the tools have no clue what to do with the inherited connections.

Anyone have ideas on how to get the inherited connections to netlist properly in amsdesigner?

Thanks,
Dan

I've done more digging and I don't think it's the inherited connections now.  I have verified that I am getting power and ground into the inverter schematic through the inherited connections.

The problem is that I still don't see output transitions when the inverter is stimulated.

I am using irun with the OSS netlister in ADE.

At this point it doesn't seem to be an ams simulator issue, but more of an internal integration problem with our 3 terminal transistor model...

But it does work fine using spectre so that's why it "feels" like an ams environment problem.

I've attached the netlist and irun log.  Thank you for taking the time to discuss my problem.  I am a new member to the forum and am excited about the ability to discuss these types of things.

Thanks!
Dan

Andrew,

I was able to discuss my issues with a member of our CAD team here and he reported that part of the problem is with our three terminal transistor model and how it netlists in OSS.  I'm told a new version of icfb will be available for us next week and I will retry it then.

We were able to get the cellview based flow to work sometimes.  Sometimes the inverter switches and sometimes it doesn't.

So it appears both our transistor model and our version of amsdesigner have problems.  

We have a work-around that circumvents these problems and I think we will be okay now.  If we get the new version of the tools and it still doesn't work, perhaps then I will upload the netlist for further analysis.

Thanks for helping out!

Best Regards,
Dan