I design a switched-capacitor filter, simulate its characteristics before layout, then I layout it by Cadence Virtuoso.

Now I want to simulate its characteristics after layout. The transient simulation is OK (by HSPICE), but I occur trouble on the simulation of PAC by SpectreRF.

Initially I rum PSS, the message say " out of memory"(the memory of our work station is 8GB), so I use swapfile command (I consult the document "Simulating Switched-Capacitor Filters with SpectreRF" from www.designers-guide.com/Analysis), then the PSS analysis is complete, no problem.

After PSS, the simulator begins to run PAC, but the problem of insufficient memory happen again. Unfortunately I can not find the similar way to solve this problem.

How to solve this problem? Or the PAC simulation after layout is not necessary; it can not give any more information?

Also, do you have multiple large-signal frequencies in your circuit, leading to a large ratio between the highest frequency and the PSS fundamental?

What is the circuit inventory saying?

Are you saving all currents, or using "subcktprobelvl" option to save currents down the hierarchy? If so, that can lead to a lot of iprobe components in the circuit inventory, which increases the memory consumption considerably. Try turning them off, or set "subcktiprobes=no" (see spectre -h options).

You can also run spectre with the "-64" command line switch to tell it to run in 64 bit mode. Or use setenv CDS_AUTO_64BIT spectre. But I'd only do that if you are simulating sensible things...

Regards,

Andrew.