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verilogA modeling advice request (Read 4598 times)
Dan Clement
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verilogA modeling advice request
Feb 04th, 2009, 8:52pm
 
Forum:

I am fairly new to verilogA and need some guidance on something with regards to simulation performance.

It is fairly common in the verificaiton work I have recently done to have statements such as the following:

@(cross(V(VDD)-4.5) or cross(V(VDD)-5.5));
if(V(VDD) < 4.5 || V(VDD) > 5.5) begin
  // code to deal with fault
end

The intention is to only use the cross to get the simulator to schedule events near where the fault occurs.  Does writing it this way cause the simulator to use min time steps to evaluate or will the if clause evaluate at each time step that is defined by the entire matrix?

The idea was to avoid having to duplicate the if statement in the initial block by doing the cross statement the way it was done.  If the if clause was embedded in the @ statement, then for sure it only executes the if when the cross triggers.  But then you have to duplicate all of the code inside of the @ in the intitial_step section to be sure that DC is covered.

Does anyone out there know which one would simulate faster?  We are doing fault checking with our verilogA models and this situation occurs in every circuit model we are creating for verification.  So add twenty or thirty of these together in a top level sim and efficiency becomes important.

Sorry for the length of the post Smiley  I also hope it made sense, it's a little late in the day...

Regards,
Dan
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Andrew Beckett
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Re: verilogA modeling advice request
Reply #1 - Feb 5th, 2009, 8:23am
 
I think that approach is reasonable. The if will be checked on every timestep, but of course it won't do anything until the crossing event occurs, or during DC. In fact until the above() function was available, you really had to do it this way.

However, it probably depends on what you want - with this approach, the if body will be executed at every time point when VDD is less than 4.5 or greater than 5.5. If you only want to detect it going out of range, you could use:

Code:
@(above(4.5-V(VDD)) or above(V(VDD)-5.5)) begin
   // code to deal with the fault
end 


I inverted the first condition so the transition will be triggered if it goes below, in fact. The benefit of the above function (compared with cross) is that it works in DC too.

Another thing to to consider is whether it is actually important to finely resolve the crossing point - or whether it's enough to just detect that the crossing occurred - if so, just having the if may be sufficient - that way the timestep is not adjusted in order to resolve the crossing point accurately. You could also use the tolerance arguments to cross (or above) to reduce the tolerance of the cross if you don't need it to be that accurate.

Regards,

Andrew.
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jbdavid
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Re: verilogA modeling advice request
Reply #2 - Feb 5th, 2009, 10:33pm
 
StackOverflow has a system where users can vote up others answers.
If we Had that HERE, I'd vote Andrew's answer up!
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rajdeep
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Re: verilogA modeling advice request
Reply #3 - Feb 19th, 2009, 7:57am
 
Hi,

How different it would have been if I had kept the if statement and hence the associated statements (for fault detection) outside cross as shown below. I have kept the cross statement to increase the preciseness.

if(V(VDD) < 4.5 || V(VDD) > 5.5)
// code for something

@(cross(V(VDD) - 4.5) or cross(V(VDD) - 5.5))
                               ;

Thnx!
Rajdeep
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Andrew Beckett
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Re: verilogA modeling advice request
Reply #4 - Feb 20th, 2009, 10:36pm
 
Not quite sure what you're asking that is any different from the first question in this thread, which I answer in the second post in this thread?

Perhaps you're asking what happens if the cross is after the if? If so, it makes no difference if the @cross is before or after the if, since the @cross causes the simulator to create a timestep shortly after the crossing point, and the if code gets evaluated regardless of its relative position to the cross in the code.

If that wasn't what you're asking, please forgive me for not guessing what you were really asking!

Andrew.
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