Forum:
I am fairly new to verilogA and need some guidance on something with regards to simulation performance.
It is fairly common in the verificaiton work I have recently done to have statements such as the following:
@(cross(V(VDD)-4.5) or cross(V(VDD)-5.5));
if(V(VDD) < 4.5 || V(VDD) > 5.5) begin
// code to deal with fault
end
The intention is to only use the cross to get the simulator to schedule events near where the fault occurs. Does writing it this way cause the simulator to use min time steps to evaluate or will the if clause evaluate at each time step that is defined by the entire matrix?
The idea was to avoid having to duplicate the if statement in the initial block by doing the cross statement the way it was done. If the if clause was embedded in the @ statement, then for sure it only executes the if when the cross triggers. But then you have to duplicate all of the code inside of the @ in the intitial_step section to be sure that DC is covered.
Does anyone out there know which one would simulate faster? We are doing fault checking with our verilogA models and this situation occurs in every circuit model we are creating for verification. So add twenty or thirty of these together in a top level sim and efficiency becomes important.
Sorry for the length of the post
I also hope it made sense, it's a little late in the day...
Regards,
Dan