I wish to build voltage limited current controlled current source using Verilog A module, to model ideal current source which is limited to supply voltage when current sink has high resistivity.

I tried using the following code, but it fails to converge for high impedance load on Isink.

any ideas how to implement such a source?


  Code:

 I(sink,src) <+ gain*I(ctrl_p,ctrl_n);

   if (V(src)>vclip) begin
      $strobe("cccs_vlimit clipping voltage as it is=:%g and clip value is:%g\n",V(sink,src),vclip);
      I(sink,src)<+ max(0, gain*I(ctrl_p,ctrl_n) + gm_nom*(V(src)-vclip));
   end //if