I need a behavioral model in Verilog-A for a sinusoidal voltage source with input random jitter. Anyone can help me? Many thanks in advance!  :)

Thanks a lot! However, I need a sinusoidal voltage source with input random jitter, while the model in your mentioned paper is only square waveform.  

The Verilog-AMS page has vco models that are simple to convert to sinusoidal output. Perhaps you can use them. For example, the model of the vco with jitter is

Code:

//
// Voltage controlled oscillator with white accumulating jitter
//

module vco2 (out, in);

input in; voltage in;				// input terminal
output out; voltage out;			// output terminal
parameter real vmin=0;				// input voltage that corresponds to minimum output frequency
parameter real vmax=vmin+1 from (vmin:inf);	// input voltage that corresponds to maximum output frequency
parameter real fmin=1 from (0:inf);		// minimum output frequency
parameter real fmax=2*fmin from (fmin:inf);	// maximum output frequency
parameter real vl=-1;				// high output voltage
parameter real vh=1;				// low output voltage
parameter real tt=0.01/fmax from (0:inf);	// output transition time
parameter real ttol=1u/fmax from (0:1/fmax);	// time tolerance
parameter real jitter=0 from [0:0.25/fmax);	// period jitter (produces white accumulating jitter)
real freq, phase, dT;
integer n, seed;

analog begin
    @(initial_step) seed = -561;

    // compute the freq from the input voltage
    freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

    // bound the frequency (this is optional)
    if (freq > fmax) freq = fmax;
    if (freq < fmin) freq = fmin;

    // add the phase noise
    freq = freq/(1 + dT*freq);

    // bound the time step to assure no cycles are skipped
    $bound_step(0.6/freq);

    // phase is the integral of the freq modulo 2p
    phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

    // update jitter twice per period
    // `M_SQRT2=sqrt(K), K=2 jitter updates/period
    @(cross(phase + `M_PI/2, +1, ttol) or cross(phase - `M_PI/2, +1, ttol)) begin
	dT = `M_SQRT2*jitter*$rdist_normal(seed,0, 1);
	n = (phase >= -`M_PI/2) && (phase < `M_PI/2);
    end

    // generate the output
    V(out) <+ transition(n ? vh : vl, 0, tt);
end
endmodule
 

To convert it to sinusoidal output, change the lines Code:

    @(cross(phase + `M_PI/2, +1, ttol) or cross(phase - `M_PI/2, +1, ttol)) begin
	dT = `M_SQRT2*jitter*$rdist_normal(seed,0, 1);
	n = (phase >= -`M_PI/2) && (phase < `M_PI/2);
    end

    // generate the output
    V(out) <+ transition(n ? vh : vl, 0, tt);
end
endmodule 

to Code:

    @(cross(phase + `M_PI/2, +1, ttol) or cross(phase - `M_PI/2, +1, ttol))
	dT = `M_SQRT2*jitter*$rdist_normal(seed,0, 1);

    // generate the output
    V(out) <+ sin(phase);
end
endmodule 

-Ken

When generating a square wave it is natural and convenient to do it twice per cycle, but it is not necessary to do it so often. Once is sufficient.

-Ken