Dear all,
  i am designing a current summing voltage refreence for and ADC . My requirement is 1.4Volt output with 50uA load curent. But when i tried simulation for load regulation using the 50ua load current my Vref is oscillationg very badly. Please some suggest me how to improve the load current variation for my requirement.

Thankx in dvance
raags

Hi,

 i  have atatched the schematic for your reference.

thanks in advance
raags

Sorry, I didn't understand it at first  :D Now, I see your point, you are trying to draw 50uA from the bandgap voltage node. No, you shouldn't do that. Think about it, as Berti says, if you try to get 50uA from that node you are subtracting it from the current that should flow into the resistor to generate the voltage level. So you are changing it. What tou should do is add some kind of buffer. Even a very small one, since 50uA is almost nothing

80uA ( or uW?) seems like a lot for a bandgap reference.. what determines the need for that current?

Raags,

I think you take the wrong approach. You should try to reduce the power consumption of your bandgap and spend that for a buffer.
I don't think that using the bandgap to drive the reference of a SAR will result in a power efficient solution.

Cheers

I agree with Berti.  You should be able to greatly reduce the current consumption in the bandgap and use the leftover for a buffer.  I don't understand your concern about using a buffer though.  You will have the PSRR modify the output of the buffer, but it is still very strongly coupled to the bandgap voltage, not the supply voltage.  In short, when your Vbg is generated from a current, that leg can have no load current, or you will have large errors.

Also, why did you choose this architecture?  Have you looked at the variation of the output due to offsets of the amplifier?  It can vary by quite a bit.  There may be other architectures that would better fit your requirements.