LeeX
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Singapore
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Hi, NiceFeng I think this is one of the high-swing cascode biasing schemes. The advantage is high output swing. In other words, every transistor is biased to the minimal Vgs it needs to stay in saturation, hence the maximum output swing is obtained at the output node.
Here is how it works, As you observed, the current through Mb1, Mb3, Mb5 is 6Ib, 4Ib and 2Ib, but the size of Mb1, Mb3, Mb5 is also 6, 4 and 2, so they have the same nominal Vgs.
For Mb2, Mb4 and Mb6, they are sized very large so their Vgs is approximately Vt.
Then, for Vm1, it is Vic-Vt, the minimal voltage needed at the drains of M1 and M2 for them to stay in saturation. And Vb1 is Vic-Vt+Vgsb3, so M3 and M4 are biased such that the voltage at their sources is Vm1. The same idea applies to Vb2.
Because Mb2, Mb4 and Mb6 have very large sizes, Mb1, Mb3, Mb5 are on the verge of saturation region.
Hope this solves your problem.
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