maxiao0116 wrote on Apr 8th, 2009, 8:39am:i set the pss fundamental freq to 400MHz and beat freq to 80MHz
No. You are wrong. Fundamental frequency is 80MHz in your case.
See
http://www.designers-guide.org/Forum/YaBB.pl?num=1232036048/4#4maxiao0116 wrote on Apr 8th, 2009, 8:39am:1. are those configurations right?
i got a pnoise plot from 100Hz@-130dBc/Hz downto 10MHz@-140dBc/Hz, almost flat!
I think your settings must be wrong for both PSS and Pnoise.
How do you set "sweeptype" in Pnoise ?
You should set like followings.
aho pss fund=80M harms=0 maxacfreq=4G errpreset=moderate annotate=status outputtype=time
boke pnoise start=10 stop=100M dec=11 maxsideband=50
+
sweeptype=relative relharmnum=1 annotate=status
maxiao0116 wrote on Apr 8th, 2009, 8:39am:2. what can i do if i want to simulate a 160MHz output frequency which doesn't have integer multiples with 400MHz sampling frequency
You don't seem to understand PSS analysis.
There is no problem if you set 80MHz as Fundamental frequency in PSS.
160MHz=2*80MHz, 400MHz=5*80MHz.
In this case you have to set
relharmnum=2.
maxiao0116 wrote on Apr 8th, 2009, 8:39am:3. what type of noise i should use in Pnoise Analysis, source?jitter?, i used source.
It is dependent on your interest.
maxiao0116 wrote on Apr 8th, 2009, 8:39am:4. if i combine the digital module and DAC together (sampling clock is generated from digital module in verilog), it seems like an oscillator,
Can i use the "Noise aware PLL flow" to convert the whole circuit to PPV based behaviour module ?
I have no answer for this since I'm not Cadence Tool's Player.
Some Cadence guys in this forum, e.g. sheldon, Andrew Beckett, Tawna Wilsey might answer for this.