I want to do the phase noise analysis of the whole PLL. And try to
get the different parts phase noise seperate.
A pss+pnoise was done for my PFD plus CHP. The inputs of the PFD is two clk which made the CHP output average current close to 0 to simulate pll lock state.The output of CHP connect to LPF. I measure the voltage of the CHP.
The resutls shows that the phase noise is very big. Around -10-dBc@1kHz.

I think there is something wrong.

I check the thread http://www.designers-guide.org/Forum/YaBB.pl?num=1036525104/0

So I can not use direct plot phase noise. So I am confused how to set the pnoise analysis for this simualtion? especially the last item (jitter ,modulated, source .......)

Thanks.

Thanks.

The discuss followed up please see:
http://www.edaboard.com/viewtopic.php?p=1139254#1139254