Hi,
I am new in Digital circuit synthesis and P&R, so I have some questions about the Standard cell application in P&R.
I finish the synthesis in DC and use the SOC encounter to do the Place and Route, but when I import the GDS2 or DEF files which output from SOC encounter to Virtuoso, there are some errors, the layout view can not display right as shown in figure 1

Only the metal 1 and metal 2 can be displayed, the Standard Cell can not be displayed. Before I import the DEF file, I have added the Symbol lib of the Standard Cell lib and imported the LEF file to the CIW. But when I open the Standard Cell layout, it is not right as shown in figure 2


Is there anything I should pay attention to when import the LEF file? I thing is there any error in the layout map, I do not use the layout map file when import these file?
Also, I can not import the Verilog, after I import the Verilog, there are only ports in the schematic, but not the symbol.
Can anyone give me some advice, please?

Thank you!
Best regards!