Hello,
I have a problem with ADSSim, when I attempt to simulate (via DynamicLink) verilog-A block, which contains simple expression         V(vout) <+ zi_nd( V(vin), {1}, {1, -1}, 50n, 0, 25n);
Neither DC no Tran analysis can't converge.
Block works right in Spectre.

Maybe anyone had similar problem.

Many Thanks.