I am attaching a paper by E. Vittoz where he exploits the feature in a Standard CMOS in his example.
Of course we need a floating well for this and assume we make use of the MOS gate to push carriers away to improve performance.
Furthermore, with the presence of gate which can be used to push carriers away from the surface, the performance for 1/f would be better than MOS.
How good a gain (beta) can we get in today's 90nm CMOS.???
Has anyone used this kind of topologies ? How much improvement do you get in 1/f noise ?
ic_engr
Edited: The attached document was removed by the forum administrator . It was "MOS Transistors Operated in the Lateral Bipolar
Mode and Their Application in CMOS Technology" by ERIC A. VITTOZ, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18, NO. 3, JUNE 1983.
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Making use of Lateral BJT in Standard triple well CMOS (Read 29 times)