Signal detection level of serial transceivers is from 65mV-ppd to 175mV-ppd, with 120mV-ppd as nominal detection threshold. (PCIE Gen2)

However, if the data pattern is clock and if there is 20dB attenuation
at baud rate, the signal amplitude will be close to 1/10 of
transmitter side full amplitude.

Assuming Tx amplitude is 1200mV-ppd, the rx side amplitude is 1/10 and close to 120mV-ppd. This signal will be rejected by input signal
detector and chip will enter electrical idle.

How we handle this?