joel
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Hi All, I'm trying to work through the cell-design tutorial bundled with Cadence Virtuoso. I'm sure this is kindergarden stuff for most of you! But I'm stuck at the LVS step.
Netlisting the schematic works fine. Creating the extracted view of the layout seems to work fine. Netlisting the extracted view fails.
From the extracted-view window, I bring up the verify/lvs form. I click the create-netlist for extracted-view, give it the appropriate names, set priority to 20 as instructed and click 'Run'.
Up comes the banner that says "Job Failed, you looser!". From Info/log I see the following error report, one for each transistor in the layout:
Cannot find switch master cell for instance +I3 in cellView (mux2 extracted) from viewlist 'auLvs extracted schematic' in library 'master'
It does this even if I use the extracted layout in the master library (supplied by Cadence), rather than the tutorial library (generated by me).
Any idea what's going wrong? What's a switch master cell? What's an auLvs view?
thnx, /jd
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