I'm building a regulator that will be used as a "controlled" pulldown for a bias node that needs to be pre-charged to VDD in some modes.  This bias node needs to be brought down to a level Vbias, which is what the pulldown regulator is for.  After it has been pulled down, the node is connected back to the bias generator.

The regulator is driving a purely capacitive load (NMOS gates).  Do you guys see any problems with the scheme below?  I've noted that it's possible, because of gate leakage and because there is no DC bias pullup for the node to drift down indefinitely, so the scheme will need to be timed so that leakage will not bring the node too low...  Do you guys see any other issues?

Also, how do I go about performing AC analysis, since there is no DC path for the output node (top of cap)?

I'm using the regulator to bring the top of cap to Vbias.

I think I need to somehow initialize the top of cap for DC bias calculation

When the switch is closed to VDD, the PFET and regulator are both turned OFF, so there is no DC current draw.

The bias generator is very high impedence, so I need the regulator to slew the cap back down to Vbias.  The bias generator is not fast enough to slew the cap.