Do designers size up the transistors according to the specs then simply hook them up in current mirrors to bias these transistors?

How do you guarantee the current mirror is giving the right bias point?

How do you know what the right bias point even is? (concerning a load transistor or tail transistor)

Hello,

Lets step back a bit.

You need to ask yourself as to why you need a bias current. Is it for speed to drive an output load, or is it in a differential amplifier to get some decent gm & gds. As you know for a diff pair the differential gain is:

A=gmi/(gdso+gdsi) ; gds=1/rds

Assume:
i: subscript for input transistor (diff pair, gmin is gm of one of them)
o:subscript for load transistor.

rds is 1/lambda*ID

Therefore you want to maintain relatively constant ID.

The current mirrors only provide bias current independent of supply voltage, process and temperature, assuming the mirroring device is in saturation, meaning VDS > VGS-VTH. The current mirror works on the principle of matched VTs & VGS. Therefore, when you connect e.g NMOS gate (M1) to a diode connected NMOS, the NMOS (M1) now mirrors the current, since the VGS and VTs are equal and acts as a current source. You can scale the mirroring current by increaseing the Width. Always make lengths equal, otherwise you will not have proper mirroring, as VT is dependent on length, channel length modulation. The only freedom designer has is the width for current mirrors.

For good mirroring you want to have long devices i.e L >> Lmin, may be 10x, otherwise matching becomes poor.

Secondly, you want to make sure for the mirroring device (M1) (current source), the VDS is relatively constant. At the least you need to make sure that the VDS > VGS-VT for worst case process and temperature. VT decreases with temperature so -20C VT will be higher. So e.g when you have a tail current on a diff pair, if the diff pair is very narrow or the dc level on inputs shifts lower due to whatever reason, the VDS on the current source (tail current) will go lower and violate the condition VDS > VGS-VT. Your current mirror will now have lower current.

The other constraint is your original source of current,  needs to be supply depedent at the least. I am referring to the one that is to be mirrored. If you use a resistor with one end on VDD and other end into a diode connected transistor, then the current into the diode is surely supply dependent, as well as process and temperature dependent.

Also the Width of the diode connected needs to be large enough such that huge variations on VGS do not occur due to change in process and temperature causing unexpected increase in the original current.

To ensure that VDS is always > VGS-VT in an actual application, its the connected circuit that needs to ensure you have enough headroom to maintain the VDS > VGS-VT for the case of diff amplifier e.g. will be your diff pair and load transistor sizes for the current you want to bias with. If e.g the VTs are very high and bias current is large you may not be able to maintain the required conditions with relatively low supply.

Secondly, you also need to ensure that rds of the transistor itself is decent.

ic_engr