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Dipankar

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forward bias diode in standard cmos process
Jun 20^th, 2009, 6:56am

Dear All,
I need to use a diode which can stay in both fwd and rev bias. The diode is in the path of current flow - none of the end connected to vss. Currently I am using a p+n diode (in nwell) provided by my PDK . I am worried about the vertical pnp (p+ (emitter)- nwell (base) - p-substrate(collector)) may raw significant amount of current (from p+ terminal to the psub) when the diode gets fwd biased. Can anybody suggest some way out ?

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With Thanks and Regards,
Dipankar.

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vivkr

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Re: forward bias diode in standard cmos process
Reply #1 - Jun 22^nd, 2009, 2:08am

Hi Dipankar,

As you have already pointed out yourself, you need to be careful about the other parasitic diodes to ensure that you don't cause them to be turned ON or trigger latchup. Another important point is that most foundries will model these well diodes etc. only for the reverse bias mode. So, if any diode properties are of interest to you (which is probably the case), then you will not be able to simulate them with any suitable amount of confidence.

I would check with the foundry if they actually allow you to use these diodes in forward mode (I doubt). You probably need a dedicated floating diode or use an available BJT as a diode.

Regards,

Vivek

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: forward bias diode in standard cmos process Reply #2 - Jun 22^nd, 2009, 3:24am hi, i think you can use diode connected pnp bjt BE junction as a forward bias diode Thanks, Rajasekhar.
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HdrChopper

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Re: forward bias diode in standard cmos process
Reply #3 - Jun 22^nd, 2009, 9:43am

Hi,

Make the substrate somehow resistive around this device so in case you get the pnp turned on the current is limited on the collector and eventually could saturate your parasitic device.

Rajasekhar, I think the pnp Dipankar is talking about cannot be diode connected, since he stated it is not connected to vss (substrate).

Regards
Tosei

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Keep it simple

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rf-design

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Reiner Franke

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Re: forward bias diode in standard cmos process
Reply #4 - Jul 11^th, 2009, 12:54am

The "parasitic" (depends on viewpoint) vertical PNP have a low beta on standard CMOS because there is typical no buried N+ on the bottom of the NWELL. So minorities does not get reflected by the increasing doping if they diffuse down. Beta is between 2-20

So for circuit simulation it mean that not all current entering the P+ are leaving the NWELL contact! So making a substrate ring does not lift up the substrate voltage. But if the NWELL is still above the substrate volatge there is no risk of triggering Latchup.

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Dipankar Community Member Offline Posts: 59	Re: forward bias diode in standard cmos process Reply #5 - Jul 11^th, 2009, 1:32am Yes, I'm not concerned abt latch-up as nwell is at a higher potential than substrate. But what I m concerned is due to the parasitic PNP some current will be leaking to substrate instead of where it should go. I planned to use a DNW beneath NW of my diode. Does it invite some other issue ? Please advise.
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rf-design

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Reiner Franke

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Re: forward bias diode in standard cmos process
Reply #6 - Jul 14^th, 2009, 12:38pm

So in your process you have a NWELL and a DeepNWELL (DNWELL)

If the DNWELL have increasing doping, that depend on the implanters energy, the beta of the lateral PNP is increased. So you have a P+ emitter surrounded by a P+collector ring. You connect the NWELL-base to the collector. So you lose only about 2% of the emitter current.

The area between the P+ emitter and the P+ collector ring could be field oxide or poly gate but not STI. Typical gate poly is used connected to emitter or a separate device pin.

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