heaven_wb wrote on Jul 6th, 2009, 1:54pm:I am designing a integer N frequency synthesizer based on CPPLL. I am confused how to design digital component. For example, PFD actually consists of D-FF and some gates. Shall I design it by verilog then synthesize it or design it in transistor level as usual? In addition, for divider, there is the same problem. The value of divider is about 2400. Is Verilog-A useful for this situation? Thank you very much.
From the question, I'd suggest you find a mentor who has gone thru this before.
The PFD should be custom not synthesized with standard cells. For jitter and lock, you have dead zones and rise/fall symmetry to worry about.
Depending on process, you'll probably need custom dividers for the first few stages (ie, CML), until standard logic is fast enough. Probably best to use custom cells there too.
I agree you'll want a higher Refclk frequency. Maybe 100MHz.
I haven't worked with Frac-N much, but sounds like a way to go.
Certainly you can and should do higher level modeling of all and parts of the loop --- matlab, verilog/verilogA, etc.
Good luck.
Wave