Geoffrey_Coram
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It might be a little tricky. I think you can get a 0th order approximation for the gate capacitance from COX W L, where COX = EPSOX / TOX. For the drain-bulk capacitance, you need to look at CJ, CJSW, CJSWG, multiplied by some function of W and the diffusion distance HDIF. However, when I look at the model card from a foundry for TOX, I see .model nch.1 NMOS ... TOX = 'toxn' ... HDIF = 'hdifn' ... CJ = cjn where toxn, hdif, and cjn are set differently for the different corners.
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