I am designing a integer N frequency synthesizer based on CPPLL. I am confused how to design digital component. For example, PFD actually consists of D-FF and some gates. Shall I design it by verilog then synthesize it or design it in transistor level as usual? In addition, for divider, there is the same problem. The value of divider is about 2400. Is Verilog-A useful for this situation? Thank you very much.

Thank you very much. The reference frequency is 1 MHz, the output frequency is 2.4GHz. another problem: can I design divider by Verilog-A? The simulator is cadence spectre. the simulation with Verilog-A seems to run, but I don't know how to deal with the information about circuit speed. verilog-A is just for simulation in mixed-signal design or can be used be synthesized into circuit? Thank you very much.

OK, Thank you very much. I will follow your idea.

Thank you very much. We will pay attention to it. Because our architecture is interger N not franctional, but we need 1-MHz spacing frequency and 2.4GHz output frequency. So the reference frequency could be only 1MHz, and divider is 2400.

heaven_wb wrote on Jul 6^th, 2009, 1:54pm:


From the question, I'd suggest you find a mentor who has gone thru this before.  
The PFD should be custom not synthesized with standard cells.  For jitter and lock, you have dead zones and rise/fall symmetry to worry about.
Depending on process, you'll probably need custom dividers for the first few stages (ie, CML), until standard logic is fast enough.  Probably best to use custom cells there too.

I agree you'll want a higher Refclk frequency.  Maybe 100MHz.  
I haven't worked with Frac-N much, but sounds like a way to go.

Certainly you can and should do higher level modeling of all and parts of the loop --- matlab, verilog/verilogA, etc.

Good luck.
Wave

oermens wrote on Jul 9^th, 2009, 3:05pm:


Basically yes.
Consider your f_T and Gm of your PMOS device.  If it's fast enough, you can use standard CMOS gates.  If not, you'll have to go to an NMOS signal path (CML).
"enough" is qualified by slew rate, with picks up noise(s) during a logic transition and creates jitter.  
PLL jitter should not be dominated by a divider.

Wave