I found the solution:

One can use the Verilog-A "delay()" function or the Verilog-AMS "absdelay()" function with the maxdelay parameter passed properly and letting the delay value be varying.


The maxdelay parameter is the key to let the delay value passed to this function be varying. If this parameter is not specified, the delay introduced by either of those functions is not allowed to vary. It seems that maxdelay is used to allocate a fixed amount of buffer space in memory to store all signal values in the delay interval.