Hello,
I'm working on a PLL design with behavioral models in VerilogAMS. I encountered a problem where it seems that the minimum timescale of 1 fs is not accurate enough to generate the exact desired frequency of my VCO.
The tuning voltage of my VCO does not get integrated to the precise value I need - namely 0V for a frequency of exactly 5.8 GHz (25MHz Fref, N = 232).
Is there any way to improve the frequency resolution by maybe circumventing the minimum timescale?
Thanks in advance,
Alexander Eßwein
Code:`timescale 1ps / 100 fs
`include "disciplines.vams"
module vco_1 (out_rf, out_div, ps, ns);
parameter real f0 = 5.8G from (0:inf); // center frequency (Hz)
// parameter real fmax = 6.3G from (0:inf);
// parameter real fmin = 5.3G from (0:inf);
parameter real kvco = 25M; // gain (Hz/V)
parameter real maxcount = 232;
input ps, ns;
//input DCO_CONTROL_S;
output out_rf, out_div;
electrical ps, ns;
//logic [7:0] DCO_CONTROL;
// logic DCO_CONTROL;
//logic DCO_CONTROL_S;
reg out_rf;
logic out_rf;
reg out_div;
logic out_div;
real vin;
// real din;
integer count;
real freq;
initial begin
out_rf = 0;
out_div = 0;
count = 0;
end //initial
always begin
vin = V(ps, ns);
#((0.5e12 / (f0 + kvco * vin))) begin
out_rf = ~out_rf;
end //delay
end
// DIV frequency generation by means of a counter
always @(posedge out_rf or negedge out_rf) begin
freq = f0 + (kvco * vin);
count = count + 1;
if (count == maxcount) begin
out_div = ~out_div;
count = 0;
end //if
end //posedge OUT_RF
endmodule