My recent work is to design a LDO for DDR I II III. Now I meet some problems. Please give me some advise.
The design aim is to design a LDO that can both sink and source current (+/- 10mA). The output voltage range is 0.75V ~ 1.25V, the output cap is 100nF (So, the output should set as the main pole), the output voltage accuracy is +/- 10mV

Because the system could both source and sink current, So, I want to know how to design a circuit that control which loop turn on

Thank you for your help

hi,
   you have specifications with you right, then start fix loop gain based on settling and you have given accuracy 10mv now find open loop gain

Thanks,
Rajasekhar.