Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Jul 16
th
, 2024, 5:34pm
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Other CAD Tools
›
Physical Verification, Extraction and Analysis
› Does Assura support hierarchical extraction?
‹
Previous topic
|
Next topic
›
Pages: 1
Does Assura support hierarchical extraction? (Read 4181 times)
ywguo
Community Fellow
Offline
Posts: 943
Shanghai, PRC
Does Assura support hierarchical extraction?
Aug 05
th
, 2009, 5:12am
Hi,
Does Assura support hierarchical extraction? The flatten extraction results a very huge netlist in post-layout simulation. It is a tedious work to find a node in the flatten netlist.
Best Regards,
Yawei
Back to top
IP Logged
Andrew Beckett
Senior Fellow
Offline
Life, don't talk to
me about Life...
Posts: 1742
Bracknell, UK
Re: Does Assura support hierarchical extraction?
Reply #1 -
Aug 15
th
, 2009, 7:01am
Yes, it does support hierarchical extraction.
Regards,
Andrew.
Back to top
IP Logged
analogue_guy
Community Member
Offline
Posts: 38
Re: Does Assura support hierarchical extraction?
Reply #2 -
Dec 16
th
, 2010, 3:12am
Hi
Would you write some hints how to setup hierarchical extraction?
BR
Back to top
IP Logged
analogue_guy
Community Member
Offline
Posts: 38
Re: Does Assura support hierarchical extraction?
Reply #3 -
Dec 17
th
, 2010, 8:37am
Ok, I applied the RTFM method ...
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
»» Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.